6 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_DDR_VER_50
13 select SYS_FSL_ERRATUM_A010315
14 select SYS_FSL_ERRATUM_A010539
21 select SYS_FSL_DDR_VER_50
22 select SYS_FSL_ERRATUM_A010539
30 select SYS_FSL_DDR_VER_50
31 select SYS_FSL_HAS_DP_DDR
44 menu "Layerscape architecture"
45 depends on FSL_LSCH2 || FSL_LSCH3
49 bool "FSL Layerscape PPA firmware support"
50 depends on !ARMV8_PSCI
51 depends on ARCH_LS1043A || ARCH_LS1046A
52 select FSL_PPA_ARMV8_PSCI
54 The FSL Primary Protected Application (PPA) is a software component
55 which is loaded during boot stage, and then remains resident in RAM
56 and runs in the TrustZone after boot.
59 config FSL_PPA_ARMV8_PSCI
60 bool "PSCI implementation in PPA firmware"
63 This config enables the ARMv8 PSCI implementation in PPA firmware.
64 This is a private PSCI implementation and different from those
65 implemented under the common ARMv8 PSCI framework.
71 config SYS_FSL_ERRATUM_A010315
72 bool "Workaround for PCIe erratum A010315"
74 config SYS_FSL_ERRATUM_A010539
75 bool "Workaround for PIN MUX erratum A010539"
78 int "Maximum number of CPUs permitted for Layerscape"
79 default 4 if ARCH_LS1043A
80 default 4 if ARCH_LS1046A
81 default 16 if ARCH_LS2080A
84 Set this number to the maximum number of possible CPUs in the SoC.
85 SoCs may have multiple clusters with each cluster may have multiple
86 ports. If some ports are reserved but higher ports are used for
87 cores, count the reserved ports. This will allocate enough memory
88 in spin table to properly handle all cores.
90 config NUM_DDR_CONTROLLERS
91 int "Maximum DDR controllers"
92 default 3 if ARCH_LS2080A
98 Enable Freescale Secure Boot feature
101 bool "Init the QSPI AHB bus"
103 The default setting for QSPI AHB bus just support 3bytes addressing.
104 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
105 bus for those flashes to support the full QSPI flash size.
107 config SYS_FSL_IFC_BANK_COUNT
108 int "Maximum banks of Integrated flash controller"
109 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
110 default 4 if ARCH_LS1043A
111 default 4 if ARCH_LS1046A
112 default 8 if ARCH_LS2080A
114 config SYS_FSL_HAS_DP_DDR
117 config SYS_FSL_SRDS_1
120 config SYS_FSL_SRDS_2
123 config SYS_HAS_SERDES
127 bool "Freescale DDR driver"
129 Select Freescale General DDR driver, shared between most Freescale
130 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
131 based Layerscape SoCs (such as ls2080a).
133 config SYS_FSL_DDR_BE
136 Access DDR registers in big-endian.
138 config SYS_FSL_DDR_LE
141 Access DDR registers in little-endian.
143 config SYS_FSL_DDR_VER
145 default 50 if SYS_FSL_DDR_VER_50
147 config SYS_FSL_DDR_VER_50
150 config SYS_FSL_DDRC_ARM_GEN3
153 config SYS_FSL_DDRC_GEN4
157 bool "Freescale DDR3 controller"
158 depends on !SYS_FSL_DDR4
160 select SYS_FSL_DDRC_ARM_GEN3
162 Enable Freescale DDR3 controller on ARM-based SoCs.
165 bool "Freescale DDR4 controller"
167 select SYS_FSL_DDRC_GEN4
169 Enable Freescale DDR4 controller.