6 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_DDR_VER_50
13 select SYS_FSL_ERRATUM_A010315
14 select SYS_FSL_ERRATUM_A010539
21 select SYS_FSL_DDR_VER_50
22 select SYS_FSL_ERRATUM_A010539
30 select SYS_FSL_DDR_VER_50
31 select SYS_FSL_HAS_DP_DDR
32 select SYS_FSL_HAS_SEC
33 select SYS_FSL_SEC_COMPAT_5
38 select SYS_FSL_HAS_SEC
39 select SYS_FSL_SEC_COMPAT_5
48 menu "Layerscape architecture"
49 depends on FSL_LSCH2 || FSL_LSCH3
53 bool "FSL Layerscape PPA firmware support"
54 depends on !ARMV8_PSCI
55 depends on ARCH_LS1043A || ARCH_LS1046A
56 select FSL_PPA_ARMV8_PSCI
58 The FSL Primary Protected Application (PPA) is a software component
59 which is loaded during boot stage, and then remains resident in RAM
60 and runs in the TrustZone after boot.
63 config FSL_PPA_ARMV8_PSCI
64 bool "PSCI implementation in PPA firmware"
67 This config enables the ARMv8 PSCI implementation in PPA firmware.
68 This is a private PSCI implementation and different from those
69 implemented under the common ARMv8 PSCI framework.
75 config SYS_FSL_ERRATUM_A010315
76 bool "Workaround for PCIe erratum A010315"
78 config SYS_FSL_ERRATUM_A010539
79 bool "Workaround for PIN MUX erratum A010539"
82 int "Maximum number of CPUs permitted for Layerscape"
83 default 4 if ARCH_LS1043A
84 default 4 if ARCH_LS1046A
85 default 16 if ARCH_LS2080A
88 Set this number to the maximum number of possible CPUs in the SoC.
89 SoCs may have multiple clusters with each cluster may have multiple
90 ports. If some ports are reserved but higher ports are used for
91 cores, count the reserved ports. This will allocate enough memory
92 in spin table to properly handle all cores.
94 config NUM_DDR_CONTROLLERS
95 int "Maximum DDR controllers"
96 default 3 if ARCH_LS2080A
102 Enable Freescale Secure Boot feature
105 bool "Init the QSPI AHB bus"
107 The default setting for QSPI AHB bus just support 3bytes addressing.
108 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
109 bus for those flashes to support the full QSPI flash size.
111 config SYS_FSL_IFC_BANK_COUNT
112 int "Maximum banks of Integrated flash controller"
113 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
114 default 4 if ARCH_LS1043A
115 default 4 if ARCH_LS1046A
116 default 8 if ARCH_LS2080A
118 config SYS_FSL_HAS_DP_DDR
121 config SYS_FSL_SRDS_1
124 config SYS_FSL_SRDS_2
127 config SYS_HAS_SERDES
131 bool "Freescale DDR driver"
133 Select Freescale General DDR driver, shared between most Freescale
134 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
135 based Layerscape SoCs (such as ls2080a).
137 config SYS_FSL_DDR_BE
140 Access DDR registers in big-endian.
142 config SYS_FSL_DDR_LE
145 Access DDR registers in little-endian.
147 config SYS_FSL_DDR_VER
149 default 50 if SYS_FSL_DDR_VER_50
151 config SYS_FSL_DDR_VER_50
154 config SYS_FSL_DDRC_ARM_GEN3
157 config SYS_FSL_DDRC_GEN4
161 bool "Freescale DDR3 controller"
162 depends on !SYS_FSL_DDR4
164 select SYS_FSL_DDRC_ARM_GEN3
166 Enable Freescale DDR3 controller on ARM-based SoCs.
169 bool "Freescale DDR4 controller"
171 select SYS_FSL_DDRC_GEN4
173 Enable Freescale DDR4 controller.