2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/errno.h>
10 #include <asm/system.h>
11 #include <asm/armv8/mmu.h>
13 #include <asm/arch/fsl_serdes.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/speed.h>
18 #include <asm/arch/mp.h>
20 #include <efi_loader.h>
22 #include <fsl-mc/fsl_mc.h>
23 #ifdef CONFIG_FSL_ESDHC
24 #include <fsl_esdhc.h>
26 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
27 #include <asm/armv8/sec_firmware.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 struct mm_region *mem_map = early_map;
34 void cpu_name(char *name)
36 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
37 unsigned int i, svr, ver;
39 svr = gur_in32(&gur->svr);
40 ver = SVR_SOC_VER(svr);
42 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
43 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
44 strcpy(name, cpu_type_list[i].name);
46 if (IS_E_PROCESSOR(svr))
49 sprintf(name + strlen(name), " Rev%d.%d",
50 SVR_MAJ(svr), SVR_MIN(svr));
54 if (i == ARRAY_SIZE(cpu_type_list))
55 strcpy(name, "unknown");
58 #ifndef CONFIG_SYS_DCACHE_OFF
60 * To start MMU before DDR is available, we create MMU table in SRAM.
61 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
62 * levels of translation tables here to cover 40-bit address space.
63 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
64 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
65 * Note, the debug print in cache_v8.c is not usable for debugging
66 * these early MMU tables because UART is not yet available.
68 static inline void early_mmu_setup(void)
70 unsigned int el = current_el();
72 /* global data is already setup, no allocation yet */
73 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
74 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
75 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
77 /* Create early page tables */
80 /* point TTBR to the new table */
81 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
82 get_tcr(el, NULL, NULL) &
83 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
86 set_sctlr(get_sctlr() | CR_M);
90 * The final tables look similar to early tables, but different in detail.
91 * These tables are in DRAM. Sub tables are added to enable cache for
94 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
95 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
97 static inline void final_mmu_setup(void)
99 u64 tlb_addr_save = gd->arch.tlb_addr;
100 unsigned int el = current_el();
101 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
107 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
108 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
111 * Only use gd->arch.secure_ram if the address is
112 * recalculated. Align to 4KB for MMU table.
114 /* put page tables in secure ram */
115 index = ARRAY_SIZE(final_map) - 2;
116 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
117 final_map[index].virt = gd->arch.secure_ram & ~0x3;
118 final_map[index].phys = final_map[index].virt;
119 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
120 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
121 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
122 tlb_addr_save = gd->arch.tlb_addr;
124 /* Use allocated (board_f.c) memory for TLB */
125 tlb_addr_save = gd->arch.tlb_allocated;
126 gd->arch.tlb_addr = tlb_addr_save;
131 /* Reset the fill ptr */
132 gd->arch.tlb_fillptr = tlb_addr_save;
134 /* Create normal system page tables */
137 /* Create emergency page tables */
138 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
139 gd->arch.tlb_emerg = gd->arch.tlb_addr;
141 gd->arch.tlb_addr = tlb_addr_save;
143 /* flush new MMU table */
144 flush_dcache_range(gd->arch.tlb_addr,
145 gd->arch.tlb_addr + gd->arch.tlb_size);
147 /* point TTBR to the new table */
148 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
151 * EL3 MMU is already enabled, just need to invalidate TLB to load the
152 * new table. The new table is compatible with the current table, if
153 * MMU somehow walks through the new table before invalidation TLB,
154 * it still works. So we don't need to turn off MMU here.
155 * When EL2 MMU table is created by calling this function, MMU needs
158 set_sctlr(get_sctlr() | CR_M);
161 u64 get_page_table_size(void)
166 int arch_cpu_init(void)
169 __asm_invalidate_dcache_all();
170 __asm_invalidate_tlb_all();
172 set_sctlr(get_sctlr() | CR_C);
182 * This function is called from common/board_r.c.
183 * It recreates MMU table in main memory.
185 void enable_caches(void)
188 __asm_invalidate_tlb_all();
194 static inline u32 initiator_type(u32 cluster, int init_id)
196 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
197 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
200 type = gur_in32(&gur->tp_ityp[idx]);
201 if (type & TP_ITYP_AV)
207 u32 cpu_pos_mask(void)
209 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
211 u32 cluster, type, mask = 0;
216 cluster = gur_in32(&gur->tp_cluster[i].lower);
217 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
218 type = initiator_type(cluster, j);
219 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
220 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
223 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
230 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
231 int i = 0, count = 0;
232 u32 cluster, type, mask = 0;
237 cluster = gur_in32(&gur->tp_cluster[i].lower);
238 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
239 type = initiator_type(cluster, j);
241 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
247 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
253 * Return the number of cores on this SOC.
255 int cpu_numcores(void)
257 return hweight32(cpu_mask());
260 int fsl_qoriq_core_to_cluster(unsigned int core)
262 struct ccsr_gur __iomem *gur =
263 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
264 int i = 0, count = 0;
270 cluster = gur_in32(&gur->tp_cluster[i].lower);
271 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
272 if (initiator_type(cluster, j)) {
279 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
281 return -1; /* cannot identify the cluster */
284 u32 fsl_qoriq_core_to_type(unsigned int core)
286 struct ccsr_gur __iomem *gur =
287 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
288 int i = 0, count = 0;
294 cluster = gur_in32(&gur->tp_cluster[i].lower);
295 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
296 type = initiator_type(cluster, j);
304 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
306 return -1; /* cannot identify the cluster */
311 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
313 return gur_in32(&gur->svr);
316 #ifdef CONFIG_DISPLAY_CPUINFO
317 int print_cpuinfo(void)
319 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
320 struct sys_info sysinfo;
322 unsigned int i, core;
323 u32 type, rcw, svr = gur_in32(&gur->svr);
328 printf(" %s (0x%x)\n", buf, svr);
329 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
330 get_sys_info(&sysinfo);
331 puts("Clock Configuration:");
332 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
335 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
336 printf("CPU%d(%s):%-4s MHz ", core,
337 type == TY_ITYP_VER_A7 ? "A7 " :
338 (type == TY_ITYP_VER_A53 ? "A53" :
339 (type == TY_ITYP_VER_A57 ? "A57" :
340 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
341 strmhz(buf, sysinfo.freq_processor[core]));
343 printf("\n Bus: %-4s MHz ",
344 strmhz(buf, sysinfo.freq_systembus));
345 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
346 #ifdef CONFIG_SYS_DPAA_FMAN
347 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
349 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
350 if (soc_has_dp_ddr()) {
351 printf(" DP-DDR: %-4s MT/s",
352 strmhz(buf, sysinfo.freq_ddrbus2));
358 * Display the RCW, so that no one gets confused as to what RCW
359 * we're actually using for this boot.
361 puts("Reset Configuration Word (RCW):");
362 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
363 rcw = gur_in32(&gur->rcwsr[i]);
365 printf("\n %08x:", i * 4);
366 printf(" %08x", rcw);
374 #ifdef CONFIG_FSL_ESDHC
375 int cpu_mmc_init(bd_t *bis)
377 return fsl_esdhc_mmc_init(bis);
381 int cpu_eth_init(bd_t *bis)
385 #ifdef CONFIG_FSL_MC_ENET
386 error = fsl_mc_ldpaa_init(bis);
388 #ifdef CONFIG_FMAN_ENET
389 fm_standard_init(bis);
394 int arch_early_init_r(void)
398 u32 psci_ver = 0xffffffff;
401 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
406 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
407 /* Check the psci version to determine if the psci is supported */
408 psci_ver = sec_firmware_support_psci_version();
410 if (psci_ver == 0xffffffff) {
411 rv = fsl_layerscape_wake_seconday_cores();
413 printf("Did not wake secondary cores\n");
417 #ifdef CONFIG_SYS_HAS_SERDES
420 #ifdef CONFIG_FMAN_ENET
428 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
429 #ifdef CONFIG_FSL_LSCH3
430 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
432 #ifdef CONFIG_LS2080A
433 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
435 #ifdef COUNTER_FREQUENCY_REAL
436 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
438 /* Update with accurate clock frequency */
439 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
442 #ifdef CONFIG_FSL_LSCH3
443 /* Enable timebase for all clusters.
444 * It is safe to do so even some clusters are not enabled.
446 out_le32(cltbenr, 0xf);
449 #ifdef CONFIG_LS2080A
451 * In certain Layerscape SoCs, the clock for each core's
452 * has an enable bit in the PMU Physical Core Time Base Enable
453 * Register (PCTBENR), which allows the watchdog to operate.
455 setbits_le32(pctbenr, 0xff);
458 /* Enable clock for timer
459 * This is a global setting.
461 out_le32(cntcr, 0x1);
466 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
468 void __efi_runtime reset_cpu(ulong addr)
472 /* Raise RESET_REQ_B */
473 val = scfg_in32(rstcr);
475 scfg_out32(rstcr, val);
478 #ifdef CONFIG_EFI_LOADER
480 void __efi_runtime EFIAPI efi_reset_system(
481 enum efi_reset_type reset_type,
482 efi_status_t reset_status,
483 unsigned long data_size, void *reset_data)
485 switch (reset_type) {
490 case EFI_RESET_SHUTDOWN:
491 /* Nothing we can do */
498 void efi_reset_system_init(void)
500 efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
505 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
507 phys_size_t ram_top = ram_size;
509 #ifdef CONFIG_SYS_MEM_TOP_HIDE
510 #error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function
513 /* Carve the MC private DRAM block from the end of DRAM */
514 #ifdef CONFIG_FSL_MC_ENET
515 ram_top -= mc_get_dram_block_size();
516 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);