2 # Copyright 2014-2015 Freescale Semiconductor
4 # SPDX-License-Identifier: GPL-2.0+
7 Freescale LayerScape with Chassis Generation 3
9 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
14 Entire DDR region splits into two regions.
15 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
16 - Region 2 is at 0x80_8000_0000 to the top of total memory,
17 for example 16GB, 0x83_ffff_ffff.
19 All DDR memory is marked as cache-enabled.
21 When MC and Debug server is enabled, they carve 512MB away from the high
22 end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
23 with MC and Debug server enabled. Linux only sees 15.5GB.
25 The reserved 512MB layout looks like
27 +---------------+ <-- top/end of memory
28 | 256MB | debug server
34 MC requires the memory to be aligned with 512MB, so even debug server is
35 not enabled, 512MB is reserved, not 256MB.
40 (1) A typical layout of various images (including Linux and other firmware images)
41 is shown below considering a 32MB NOR flash device present on most
42 pre-silicon platforms (simulator and emulator):
44 -------------------------
46 | (linux + DTB + RFS) |
47 ------------------------- ----> 0x0120_0000
49 ------------------------- ----> 0x00C0_0000
51 ------------------------- ----> 0x0070_0000
53 ------------------------- ----> 0x006C_0000
55 ------------------------- ----> 0x0020_0000
57 ------------------------- ----> 0x0000_1000
59 ------------------------- ----> 0x0000_0080
61 ------------------------- ----> 0x0000_0000
63 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
65 (2) A typical layout of various images (including Linux and other firmware images)
66 is shown below considering a 128MB NOR flash device present on QDS and RDB
68 ----------------------------------------- ----> 0x5_8800_0000 ---
69 | .. Unused .. (7M) | |
70 ----------------------------------------- ----> 0x5_8790_0000 |
71 | FIT Image (linux + DTB + RFS) (40M) | |
72 ----------------------------------------- ----> 0x5_8510_0000 |
73 | PHY firmware (2M) | |
74 ----------------------------------------- ----> 0x5_84F0_0000 | 64K
75 | Debug Server FW (2M) | | Alt
76 ----------------------------------------- ----> 0x5_84D0_0000 | Bank
78 ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
79 | MC DPC Blob (1M) | |
80 ----------------------------------------- ----> 0x5_8480_0000 |
81 | MC DPL Blob (1M) | |
82 ----------------------------------------- ----> 0x5_8470_0000 |
84 ----------------------------------------- ----> 0x5_8430_0000 |
85 | BootLoader Environment (1M) | |
86 ----------------------------------------- ----> 0x5_8420_0000 |
88 ----------------------------------------- ----> 0x5_8410_0000 |
89 | RCW and PBI (1M) | |
90 ----------------------------------------- ----> 0x5_8400_0000 ---
91 | .. Unused .. (7M) | |
92 ----------------------------------------- ----> 0x5_8390_0000 |
93 | FIT Image (linux + DTB + RFS) (40M) | |
94 ----------------------------------------- ----> 0x5_8110_0000 |
95 | PHY firmware (2M) | |
96 ----------------------------------------- ----> 0x5_80F0_0000 | 64K
97 | Debug Server FW (2M) | | Bank
98 ----------------------------------------- ----> 0x5_80D0_0000 |
100 ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
101 | MC DPC Blob (1M) | |
102 ----------------------------------------- ----> 0x5_8080_0000 |
103 | MC DPL Blob (1M) | |
104 ----------------------------------------- ----> 0x5_8070_0000 |
106 ----------------------------------------- ----> 0x5_8030_0000 |
107 | BootLoader Environment (1M) | |
108 ----------------------------------------- ----> 0x5_8020_0000 |
109 | BootLoader (1M) | |
110 ----------------------------------------- ----> 0x5_8010_0000 |
111 | RCW and PBI (1M) | |
112 ----------------------------------------- ----> 0x5_8000_0000 ---
114 128-MB NOR flash layout for QDS and RDB boards
116 Environment Variables
117 =====================
118 mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
119 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
121 mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value
122 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
124 mcinitcmd: This environment variable is defined to initiate MC and DPL deployment
125 from the location where it is stored(NOR, NAND, SD, SATA, USB)during
126 u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR
127 will be null and MC will not be booted and DPL will not be applied
128 during U-boot booting.However the MC, DPC and DPL can be applied from
129 console independently.
130 The variable needs to be set from the console once and then on
131 rebooting the parameters set in the variable will automatically be
132 executed. The commmand is demostrated taking an example of mc boot
133 using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash:
135 cp.b 0xa0000000 0x580300000 $filesize
136 cp.b 0x80000000 0x580800000 $filesize
137 cp.b 0x90000000 0x580700000 $filesize
139 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000'
141 If only linux is to be booted then the mcinitcmd environment should be set as
143 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
145 Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
146 MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000
147 and 0x580700000 are addresses in NOR where these are copied. It is to be
148 noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000'
149 can be replaced with the addresses of DDR to
150 which these will be copied in case of these binaries being stored in other
151 devices like SATA, USB, NAND, SD etc.
155 Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
156 The difference between NAND boot RCW image and NOR boot image is the PBI
157 command sequence. Below is one example for PBI commands for LS2085AQDS which
158 uses NAND device with 2KB/page, block size 128KB.
160 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
161 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
162 The above two commands set bootloc register to 0x00000000_1800a000 where
163 the u-boot code will be running in OCRAM.
165 3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
166 BLOCK_SIZE=0x00014000
167 This command copies u-boot image from NAND device into OCRAM. The values need
168 to adjust accordingly.
170 SRC should match the cfg_rcw_src, the reset config pins. It depends
171 on the NAND device. See reference manual for cfg_rcw_src.
172 SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In
173 the example above, 128KB. For easy maintenance, we put it at
174 the beginning of next block from RCW.
175 DEST_ADDR is fixed at 0x1800a000, matching bootloc set above.
176 BLOCK_SIZE is the size to be copied by PBI.
178 RCW image should be written to the beginning of NAND device. Example of using
181 nand write <rcw image in memory> 0 <size of rcw image>
183 To form the NAND image, build u-boot with NAND config, for example,
184 ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
185 The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
187 nand write <u-boot image in memory> 200000 <size of u-boot image>
189 With these two images in NAND device, the board can boot from NAND.
191 Another example for LS2085ARDB boards,
193 1) CCSR 4-byte write to 0x00e00404, data=0x00000000
194 2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
195 3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
196 BLOCK_SIZE=0x00014000
198 nand write <rcw image in memory> 0 <size of rcw image>
199 nand write <u-boot image in memory> 80000 <size of u-boot image>
201 Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
202 to match board NAND device with 4KB/page, block size 512KB.
204 Note, LS2088A and LS1088A don't support booting from NAND.
208 Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin.
209 The difference between SD boot RCW image and QSPI-NOR boot image is the
210 PBI command sequence. Below is one example for PBI commands for RDB
211 and QDS which uses SD device with block size 512. Block location can be
212 calculated by dividing offset with block size.
214 1) Block Copy: SRC=0x0040, SRC_ADDR=0x00100000, DEST_ADDR=0x1800a000,
215 BLOCK_SIZE=0x00016000
217 This command copies u-boot image from SD device into OCRAM. The values
218 need to adjust accordingly for SD/eMMC
220 SRC should match the cfg_rcw_src, the reset config pins.
221 The value for source(SRC) can be 0x0040 or 0x0041
222 depending upon SD or eMMC.
223 SRC_ADDR is the offset of u-boot-with-spl.bin image in SD device.
224 In the example above, 1MB. This is same as QSPI-NOR.
225 DEST_ADDR is configured at 0x1800a000, matching bootloc set above.
226 BLOCK_SIZE is the size to be copied by PBI.
228 2) CCSR 4-byte write to 0x01e00404, data=0x00000000
229 3) CCSR 4-byte write to 0x01e00400, data=0x1800a000
230 The above two commands set bootloc register to 0x00000000_1800a000 where
231 the u-boot code will be running in OCRAM.
234 RCW image should be written at 8th block of device(SD/eMMC). Example of
238 mmc write <rcw image in memory> 0x8 <size of rcw in block count typical value=10>
240 To form the SD-Boot image, build u-boot with SD config, for example,
241 ls1088ardb_sdcard_qspi_defconfig. The image needed is u-boot-with-spl.bin.
242 The u-boot image should be written to match SRC_ADDR, in above example
243 offset 0x100000 in other work it means block location 0x800
245 mmc erase 0x800 0x1800
246 mmc write <u-boot image in memory> 0x800 <size of u-boot image in block count>
248 With these two images in SD/eMMC device, the board can boot from SD/eMMC.
250 MMU Translation Tables
251 ======================
253 (1) Early MMU Tables:
255 Level 0 Level 1 Level 2
256 ------------------ ------------------ ------------------
257 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
258 ------------------ ------------------ ------------------
259 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
260 ------------------ | ------------------ ------------------
261 | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
262 ------------------ | ------------------ ------------------
263 | | 0x00_c000_0000 | | 0x00_0060_0000 |
264 | ------------------ ------------------
265 | | 0x01_0000_0000 | | 0x00_0080_0000 |
266 | ------------------ ------------------
269 | | 0x05_8000_0000 | --|
270 | ------------------ |
271 | | 0x05_c000_0000 | |
272 | ------------------ |
274 | ------------------ | ------------------
275 |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 |
276 ------------------ ------------------
277 | 0x80_4000_0000 | | 0x00_3020_0000 |
278 ------------------ ------------------
279 | 0x80_8000_0000 | | 0x00_3040_0000 |
280 ------------------ ------------------
281 | 0x80_c000_0000 | | 0x00_3060_0000 |
282 ------------------ ------------------
283 | 0x81_0000_0000 | | 0x00_3080_0000 |
284 ------------------ ------------------
287 (2) Final MMU Tables:
289 Level 0 Level 1 Level 2
290 ------------------ ------------------ ------------------
291 | 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 |
292 ------------------ ------------------ ------------------
293 | 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 |
294 ------------------ | ------------------ ------------------
295 | invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 |
296 ------------------ | ------------------ ------------------
297 | | 0x00_c000_0000 | | 0x00_0060_0000 |
298 | ------------------ ------------------
299 | | 0x01_0000_0000 | | 0x00_0080_0000 |
300 | ------------------ ------------------
303 | | 0x08_0000_0000 | --|
304 | ------------------ |
305 | | 0x08_4000_0000 | |
306 | ------------------ |
308 | ------------------ | ------------------
309 |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 |
310 ------------------ ------------------
311 | 0x80_4000_0000 | | 0x08_0020_0000 |
312 ------------------ ------------------
313 | 0x80_8000_0000 | | 0x08_0040_0000 |
314 ------------------ ------------------
315 | 0x80_c000_0000 | | 0x08_0060_0000 |
316 ------------------ ------------------
317 | 0x81_0000_0000 | | 0x08_0080_0000 |
318 ------------------ ------------------
322 DPAA2 commands to manage Management Complex (MC)
323 ------------------------------------------------
324 DPAA2 commands has been introduced to manage Management Complex
325 (MC). These commands are used to start mc, aiop and apply DPL
326 from u-boot command prompt.
328 Please note Management complex Firmware(MC), DPL and DPC are no
329 more deployed during u-boot boot-sequence.
332 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
333 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
334 c) fsl_mc start aiop <FW_addr> - Start AIOP
336 How to use commands :-
337 1. Command sequence for u-boot ethernet:
338 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
339 b) DPMAC net-devices are now available for use
342 Assumption: MC firmware, DPL and DPC dtb is already programmed
345 => fsl_mc start mc 580300000 580800000
346 => setenv ethact DPMAC1@xgmii
349 2. Command sequence for Linux boot:
350 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
351 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
352 c) No DPMAC net-devices are available for use in u-boot
356 Assumption: MC firmware, DPL and DPC dtb is already programmed
359 => fsl_mc start mc 580300000 580800000
360 => setenv ethact DPMAC1@xgmii
361 => tftp a0000000 kernel.itb
362 => fsl_mc apply dpl 580700000
365 3. Command sequence for AIOP boot:
366 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
367 b) fsl_mc start aiop <FW_addr> - Start AIOP
368 c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
369 d) No DPMAC net-devices are availabe for use in u-boot
370 Please note actual AIOP start will happen during DPL parsing of
374 Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
375 programmed on NOR flash.
377 => fsl_mc start mc 580300000 580800000
378 => fsl_mc start aiop 0x580900000
379 => setenv ethact DPMAC1@xgmii
380 => fsl_mc apply dpl 580700000
384 If the core runs at higher than x3 speed of the platform, there is
385 possiblity about sev instruction to getting missed by other cores.
386 This is because of SoC Run Control block may not able to sample
387 the EVENTI(Sev) signals.
389 Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
392 Errata workaround uses Env variable "a009635_interval_val". It uses decimal
394 - Default value of env variable is platform clock (MHz)
396 - User can modify default value by updating the env variable
397 setenv a009635_interval_val 600; saveenv;
398 It configure platform clock as 600 MHz
400 - Env variable as 0 signifies no workaround