2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
11 #include <asm/arch/soc.h>
13 #ifdef CONFIG_SYS_FSL_SRDS_1
14 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
17 int is_serdes_configured(enum srds_prtcl device)
21 #ifdef CONFIG_SYS_FSL_SRDS_1
22 ret |= serdes1_prtcl_map[device];
28 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
30 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
31 u32 cfg = gur_in32(&gur->rcwsr[4]);
35 #ifdef CONFIG_SYS_FSL_SRDS_1
37 cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
38 cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
42 printf("invalid SerDes%d\n", sd);
46 /* Is serdes enabled at all? */
47 if (unlikely(cfg == 0))
50 for (i = 0; i < SRDS_MAX_LANES; i++) {
51 if (serdes_get_prtcl(sd, cfg, i) == device)
58 int get_serdes_protocol(void)
60 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
61 u32 cfg = gur_in32(&gur->rcwsr[4]) &
62 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
63 cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
68 const char *serdes_clock_to_string(u32 clock)
71 case SRDS_PLLCR0_RFCK_SEL_100:
73 case SRDS_PLLCR0_RFCK_SEL_125:
75 case SRDS_PLLCR0_RFCK_SEL_156_25:
82 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
83 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
85 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
89 memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
91 cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
92 cfg >>= sd_prctl_shift;
93 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
95 if (!is_serdes_prtcl_valid(sd, cfg))
96 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
98 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
99 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
101 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
102 debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
104 serdes_prtcl_map[lane_prtcl] = 1;
108 void fsl_serdes_init(void)
110 #ifdef CONFIG_SYS_FSL_SRDS_1
111 serdes_init(FSL_SRDS_1,
112 CONFIG_SYS_FSL_SERDES_ADDR,
113 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
114 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,