git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <linux/errno.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/arch/soc.h>
  12 #include <fsl-mc/ldpaa_wriop.h>
  13
  14 #ifdef CONFIG_SYS_FSL_SRDS_1
  15 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  16 #endif
  17 #ifdef CONFIG_SYS_FSL_SRDS_2
  18 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  19 #endif
  20
  21 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  22 int xfi_dpmac[XFI8 + 1];
  23 int sgmii_dpmac[SGMII16 + 1];
  24 #endif
  25
  26 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
  27 {
  28         return;
  29 }
  30
  31 /*
  32  *The return value of this func is the serdes protocol used.
  33  *Typically this function is called number of times depending
  34  *upon the number of serdes blocks in the Silicon.
  35  *Zero is used to denote that no serdes was enabled,
  36  *this is the case when golden RCW was used where DPAA2 bring was
  37  *intentionally removed to achieve boot to prompt
  38 */
  39
  40 __weak int serdes_get_number(int serdes, int cfg)
  41 {
  42         return cfg;
  43 }
  44
  45 int is_serdes_configured(enum srds_prtcl device)
  46 {
  47         int ret = 0;
  48
  49 #ifdef CONFIG_SYS_FSL_SRDS_1
  50         if (!serdes1_prtcl_map[NONE])
  51                 fsl_serdes_init();
  52
  53         ret |= serdes1_prtcl_map[device];
  54 #endif
  55 #ifdef CONFIG_SYS_FSL_SRDS_2
  56         if (!serdes2_prtcl_map[NONE])
  57                 fsl_serdes_init();
  58
  59         ret |= serdes2_prtcl_map[device];
  60 #endif
  61
  62         return !!ret;
  63 }
  64
  65 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  66 {
  67         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  68         u32 cfg = 0;
  69         int i;
  70
  71         switch (sd) {
  72 #ifdef CONFIG_SYS_FSL_SRDS_1
  73         case FSL_SRDS_1:
  74                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
  75                 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
  76                 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
  77                 break;
  78 #endif
  79 #ifdef CONFIG_SYS_FSL_SRDS_2
  80         case FSL_SRDS_2:
  81                 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
  82                 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
  83                 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
  84                 break;
  85 #endif
  86         default:
  87                 printf("invalid SerDes%d\n", sd);
  88                 break;
  89         }
  90
  91         cfg = serdes_get_number(sd, cfg);
  92
  93         /* Is serdes enabled at all? */
  94         if (cfg == 0)
  95                 return -ENODEV;
  96
  97         for (i = 0; i < SRDS_MAX_LANES; i++) {
  98                 if (serdes_get_prtcl(sd, cfg, i) == device)
  99                         return i;
 100         }
 101
 102         return -ENODEV;
 103 }
 104
 105 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 106                  u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 107 {
 108         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 109         u32 cfg;
 110         int lane;
 111
 112         if (serdes_prtcl_map[NONE])
 113                 return;
 114
 115         memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
 116
 117         cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
 118         cfg >>= sd_prctl_shift;
 119
 120         cfg = serdes_get_number(sd, cfg);
 121         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
 122
 123         if (!is_serdes_prtcl_valid(sd, cfg))
 124                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
 125
 126         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 127                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
 128                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
 129                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
 130                 else {
 131                         serdes_prtcl_map[lane_prtcl] = 1;
 132 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 133                         switch (lane_prtcl) {
 134                         case QSGMII_A:
 135                         case QSGMII_B:
 136                         case QSGMII_C:
 137                         case QSGMII_D:
 138                                 wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
 139                                 break;
 140                         default:
 141                                 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
 142                                         wriop_init_dpmac(sd,
 143                                                          xfi_dpmac[lane_prtcl],
 144                                                          (int)lane_prtcl);
 145
 146                                  if (lane_prtcl >= SGMII1 &&
 147                                      lane_prtcl <= SGMII16)
 148                                         wriop_init_dpmac(sd, sgmii_dpmac[
 149                                                          lane_prtcl],
 150                                                          (int)lane_prtcl);
 151                                 break;
 152                         }
 153 #endif
 154                 }
 155         }
 156
 157         /* Set the first element to indicate serdes has been initialized */
 158         serdes_prtcl_map[NONE] = 1;
 159 }
 160
 161 void fsl_serdes_init(void)
 162 {
 163 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 164         int i , j;
 165
 166         for (i = XFI1, j = 1; i <= XFI8; i++, j++)
 167                 xfi_dpmac[i] = j;
 168
 169         for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
 170                 sgmii_dpmac[i] = j;
 171 #endif
 172
 173 #ifdef CONFIG_SYS_FSL_SRDS_1
 174         serdes_init(FSL_SRDS_1,
 175                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
 176                     FSL_CHASSIS3_SRDS1_REGSR,
 177                     FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 178                     FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
 179                     serdes1_prtcl_map);
 180 #endif
 181 #ifdef CONFIG_SYS_FSL_SRDS_2
 182         serdes_init(FSL_SRDS_2,
 183                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 184                     FSL_CHASSIS3_SRDS2_REGSR,
 185                     FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 186                     FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
 187                     serdes2_prtcl_map);
 188 #endif
 189 }