2 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
6 * Extracted from armv8/start.S
10 #include <linux/linkage.h>
12 #include <asm/macro.h>
14 #include <asm/arch/mp.h>
16 #ifdef CONFIG_FSL_LSCH3
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/u-boot.h>
23 mov x29, lr /* Save LR */
25 #ifdef CONFIG_FSL_LSCH3
27 /* Set Wuo bit for RN-I 20 */
29 ldr x0, =CCI_AUX_CONTROL_BASE(20)
34 /* Add fully-coherent masters to DVM domain */
36 ldr x1, =CCI_MN_RNF_NODEID_LIST
37 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
38 bl ccn504_add_masters_to_dvm
40 /* Set all RN-I ports to QoS of 15 */
41 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
44 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
47 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
51 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
54 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
57 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
61 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
64 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
67 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
71 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
74 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
77 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
81 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
84 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
87 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
91 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
94 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
97 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
103 /* Set the SMMU page size in the sACR register */
106 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
110 /* Initialize GIC Secure Bank Status */
111 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
112 branch_if_slave x0, 1f
118 bl gic_init_secure_percpu
119 #elif defined(CONFIG_GICV2)
122 bl gic_init_secure_percpu
126 branch_if_master x0, x1, 2f
128 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
129 ldr x0, =secondary_boot_func
134 #ifdef CONFIG_FSL_TZPC_BP147
135 /* Set Non Secure access for all devices protected via TZPC */
136 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
137 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
144 #ifdef CONFIG_FSL_TZASC_400
146 * LS2080 and its personalities does not support TZASC
147 * So skip TZASC related operations
151 ldr w1, =SVR_DEV_LS2080A
155 /* Set TZASC so that:
156 * a. We use only Region0 whose global secure write/read is EN
157 * b. We use only Region0 whose NSAID write/read is EN
159 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
162 ldr x1, =TZASC_GATE_KEEPER(0)
163 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
164 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
167 ldr x1, =TZASC_GATE_KEEPER(1)
168 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
169 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
172 ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
173 ldr w0, [x1] /* Region-0 Attributes Register */
174 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
175 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
178 ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
179 ldr w0, [x1] /* Region-1 Attributes Register */
180 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
181 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
184 ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
185 ldr w0, [x1] /* Region-0 Access Register */
186 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
189 ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
190 ldr w0, [x1] /* Region-1 Attributes Register */
191 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
198 #ifdef CONFIG_ARCH_LS1046A
199 /* Initialize the L2 RAM latency */
200 mrs x1, S3_1_c11_c0_2
202 /* Clear L2 Tag RAM latency and L2 Data RAM latency */
204 /* Set L2 data ram latency bits [2:0] */
206 /* set L2 tag ram latency bits [8:6] */
208 msr S3_1_c11_c0_2, x1
212 mov lr, x29 /* Restore LR */
214 ENDPROC(lowlevel_init)
216 #ifdef CONFIG_FSL_LSCH3
219 ldr x1, =FSL_LSCH3_SVR
224 /* x0 has the desired status, return 0 for success, 1 for timeout
225 * clobber x1, x2, x3, x4, x6, x7
228 mov x7, #0 /* flag for timeout */
229 mrs x3, cntpct_el0 /* read timer */
230 add x3, x3, #1200 /* timeout after 100 microseconds */
232 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
233 mov w6, #8 /* HN-F node count */
236 cmp x2, x1 /* check status */
241 mov x7, #1 /* timeout */
244 add x0, x0, #0x10000 /* move to next node */
252 /* x0 has the desired state, clobber x1, x2, x6 */
254 /* power state to SFONLY */
255 mov w6, #8 /* HN-F node count */
257 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
258 1: /* set pstate to sfonly */
260 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
263 add x0, x0, #0x10000 /* move to next node */
269 ENTRY(__asm_flush_l3_dcache)
271 * Return status in x0
273 * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
279 mov x0, #0x1 /* HNFPSTAT_SFONLY */
282 mov x0, #0x4 /* SFONLY status */
285 mov x8, #1 /* timeout */
288 mov x0, #0x3 /* HNFPSTAT_FAM */
291 mov x0, #0xc /* FAM status */
299 ENDPROC(__asm_flush_l3_dcache)
303 /* Keep literals not used by the secondary boot code outside it */
306 /* Using 64 bit alignment since the spin table is accessed as data */
308 .global secondary_boot_code
309 /* Secondary Boot Code starts here */
313 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
316 ENTRY(secondary_boot_func)
319 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
320 * MPIDR[7:2] = AFF0_RES
321 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
322 * MPIDR[23:16] = AFF2_CLUSTERID
324 * MPIDR[29:25] = RES0
327 * MPIDR[39:32] = AFF3
329 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
330 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
331 * until AFF2_CLUSTERID and AFF3 have non-zero values)
333 * LPID = MPIDR[15:8] | MPIDR[1:0]
338 orr x10, x2, x1, lsl #2 /* x10 has LPID */
339 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
341 * offset of the spin table element for this core from start of spin
342 * table (each elem is padded to 64 bytes)
345 ldr x0, =__spin_table
346 /* physical address of this cpus spin table element */
349 ldr x0, =__real_cntfrq
351 msr cntfrq_el0, x0 /* set with real frequency */
352 str x9, [x11, #16] /* LPID */
354 str x4, [x11, #8] /* STATUS */
356 #if defined(CONFIG_GICV3)
357 gic_wait_for_interrupt_m x0
358 #elif defined(CONFIG_GICV2)
360 gic_wait_for_interrupt_m x0, w1
367 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
372 tbz x1, #25, cpu_is_le
373 rev x0, x0 /* BE to LE conversion */
376 ldr x6, =IH_ARCH_DEFAULT
380 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
381 adr x3, secondary_switch_to_el1
382 ldr x4, =ES_TO_AARCH64
385 ldr x4, =ES_TO_AARCH32
387 bl secondary_switch_to_el2
390 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
391 adr x3, secondary_switch_to_el1
395 ldr x4, =ES_TO_AARCH64
396 bl secondary_switch_to_el2
398 ENDPROC(secondary_boot_func)
400 ENTRY(secondary_switch_to_el2)
401 switch_el x5, 1f, 0f, 0f
403 1: armv8_switch_to_el2_m x3, x4, x5
404 ENDPROC(secondary_switch_to_el2)
406 ENTRY(secondary_switch_to_el1)
410 orr x10, x2, x1, lsl #2 /* x10 has LPID */
413 ldr x0, =__spin_table
414 /* physical address of this cpus spin table element */
420 ldr x6, =IH_ARCH_DEFAULT
424 ldr x4, =ES_TO_AARCH32
427 2: ldr x4, =ES_TO_AARCH64
430 switch_el x5, 0f, 1f, 0f
432 1: armv8_switch_to_el1_m x3, x4, x5
433 ENDPROC(secondary_switch_to_el1)
435 /* Ensure that the literals used by the secondary boot code are
436 * assembled within it (this is required so that we can protect
437 * this area with a single memreserve region
441 /* 64 bit alignment for elements accessed as data */
443 .global __real_cntfrq
445 .quad COUNTER_FREQUENCY
446 .globl __secondary_boot_code_size
447 .type __secondary_boot_code_size, %object
448 /* Secondary Boot Code ends here */
449 __secondary_boot_code_size:
450 .quad .-secondary_boot_code