2 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
6 * Extracted from armv8/start.S
10 #include <linux/linkage.h>
12 #include <asm/macro.h>
13 #include <asm/arch-fsl-layerscape/soc.h>
15 #include <asm/arch/mp.h>
17 #ifdef CONFIG_FSL_LSCH3
18 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
20 #include <asm/u-boot.h>
23 * For LS1043a rev1.0, GIC base address align with 4k.
24 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
25 * is set, GIC base address align with 4K, or else align
28 * x0: the base address of GICD
29 * x1: the base address of GICC
36 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
37 ldr x2, =DCFG_CCSR_SVR
41 ands w3, w3, #SVR_WO_E << 8
42 mov w4, #SVR_LS1043A << 8
48 ldr x2, =SCFG_GIC400_ALIGN
51 tbnz w2, #GIC_ADDR_BIT, 1f
52 ldr x0, =GICD_BASE_64K
54 ldr x1, =GICC_BASE_64K
59 ENDPROC(get_gic_offset)
61 ENTRY(smp_kick_all_cpus)
62 /* Kick secondary cpus up by SGI 0 interrupt */
63 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
64 mov x29, lr /* Save LR */
66 bl gic_kick_secondary_cpus
67 mov lr, x29 /* Restore LR */
70 ENDPROC(smp_kick_all_cpus)
74 mov x29, lr /* Save LR */
76 #ifdef CONFIG_FSL_LSCH3
78 /* Set Wuo bit for RN-I 20 */
80 ldr x0, =CCI_AUX_CONTROL_BASE(20)
85 * Set forced-order mode in RNI-6, RNI-20
86 * This is required for performance optimization on LS2088A
87 * LS2080A family does not support setting forced-order mode,
88 * so skip this operation for LS2080A family
92 ldr w1, =SVR_DEV_LS2080A
96 ldr x0, =CCI_AUX_CONTROL_BASE(6)
99 ldr x0, =CCI_AUX_CONTROL_BASE(20)
105 /* Add fully-coherent masters to DVM domain */
107 ldr x1, =CCI_MN_RNF_NODEID_LIST
108 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
109 bl ccn504_add_masters_to_dvm
111 /* Set all RN-I ports to QoS of 15 */
112 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
115 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
118 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
122 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
125 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
128 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
132 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
135 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
138 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
142 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
145 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
148 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
152 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
155 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
158 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
162 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
165 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
168 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
174 /* Set the SMMU page size in the sACR register */
177 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
181 /* Initialize GIC Secure Bank Status */
182 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
183 branch_if_slave x0, 1f
189 bl gic_init_secure_percpu
190 #elif defined(CONFIG_GICV2)
192 bl gic_init_secure_percpu
196 branch_if_master x0, x1, 2f
198 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
199 ldr x0, =secondary_boot_func
204 #ifdef CONFIG_FSL_TZPC_BP147
205 /* Set Non Secure access for all devices protected via TZPC */
206 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
207 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
214 #ifdef CONFIG_FSL_TZASC_400
216 * LS2080 and its personalities does not support TZASC
217 * So skip TZASC related operations
221 ldr w1, =SVR_DEV_LS2080A
225 /* Set TZASC so that:
226 * a. We use only Region0 whose global secure write/read is EN
227 * b. We use only Region0 whose NSAID write/read is EN
229 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
232 ldr x1, =TZASC_GATE_KEEPER(0)
233 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
234 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
237 ldr x1, =TZASC_GATE_KEEPER(1)
238 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
239 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
242 ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
243 ldr w0, [x1] /* Region-0 Attributes Register */
244 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
245 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
248 ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
249 ldr w0, [x1] /* Region-1 Attributes Register */
250 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
251 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
254 ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
255 ldr w0, [x1] /* Region-0 Access Register */
256 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
259 ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
260 ldr w0, [x1] /* Region-1 Attributes Register */
261 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
268 #ifdef CONFIG_ARCH_LS1046A
269 /* Initialize the L2 RAM latency */
270 mrs x1, S3_1_c11_c0_2
272 /* Clear L2 Tag RAM latency and L2 Data RAM latency */
274 /* Set L2 data ram latency bits [2:0] */
276 /* set L2 tag ram latency bits [8:6] */
278 msr S3_1_c11_c0_2, x1
282 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
286 mov lr, x29 /* Restore LR */
288 ENDPROC(lowlevel_init)
290 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
291 ENTRY(fsl_ocram_init)
292 mov x28, lr /* Save LR */
294 bl fsl_ocram_clear_ecc_err
295 mov lr, x28 /* Restore LR */
297 ENDPROC(fsl_ocram_init)
299 ENTRY(fsl_clear_ocram)
301 ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
302 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
310 ENDPROC(fsl_clear_ocram)
312 ENTRY(fsl_ocram_clear_ecc_err)
313 /* OCRAM1/2 ECC status bit */
315 ldr x0, =DCSR_DCFG_SBEESR2
317 ldr x0, =DCSR_DCFG_MBEESR2
320 ENDPROC(fsl_ocram_init)
323 #ifdef CONFIG_FSL_LSCH3
326 ldr x1, =FSL_LSCH3_SVR
331 /* x0 has the desired status, return 0 for success, 1 for timeout
332 * clobber x1, x2, x3, x4, x6, x7
335 mov x7, #0 /* flag for timeout */
336 mrs x3, cntpct_el0 /* read timer */
337 add x3, x3, #1200 /* timeout after 100 microseconds */
339 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
340 mov w6, #8 /* HN-F node count */
343 cmp x2, x1 /* check status */
348 mov x7, #1 /* timeout */
351 add x0, x0, #0x10000 /* move to next node */
359 /* x0 has the desired state, clobber x1, x2, x6 */
361 /* power state to SFONLY */
362 mov w6, #8 /* HN-F node count */
364 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
365 1: /* set pstate to sfonly */
367 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
370 add x0, x0, #0x10000 /* move to next node */
376 ENTRY(__asm_flush_l3_dcache)
378 * Return status in x0
380 * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
386 mov x0, #0x1 /* HNFPSTAT_SFONLY */
389 mov x0, #0x4 /* SFONLY status */
392 mov x8, #1 /* timeout */
395 mov x0, #0x3 /* HNFPSTAT_FAM */
398 mov x0, #0xc /* FAM status */
406 ENDPROC(__asm_flush_l3_dcache)
410 /* Keep literals not used by the secondary boot code outside it */
413 /* Using 64 bit alignment since the spin table is accessed as data */
415 .global secondary_boot_code
416 /* Secondary Boot Code starts here */
420 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
423 ENTRY(secondary_boot_func)
426 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
427 * MPIDR[7:2] = AFF0_RES
428 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
429 * MPIDR[23:16] = AFF2_CLUSTERID
431 * MPIDR[29:25] = RES0
434 * MPIDR[39:32] = AFF3
436 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
437 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
438 * until AFF2_CLUSTERID and AFF3 have non-zero values)
440 * LPID = MPIDR[15:8] | MPIDR[1:0]
445 orr x10, x2, x1, lsl #2 /* x10 has LPID */
446 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
448 * offset of the spin table element for this core from start of spin
449 * table (each elem is padded to 64 bytes)
452 ldr x0, =__spin_table
453 /* physical address of this cpus spin table element */
456 ldr x0, =__real_cntfrq
458 msr cntfrq_el0, x0 /* set with real frequency */
459 str x9, [x11, #16] /* LPID */
461 str x4, [x11, #8] /* STATUS */
463 #if defined(CONFIG_GICV3)
464 gic_wait_for_interrupt_m x0
465 #elif defined(CONFIG_GICV2)
468 gic_wait_for_interrupt_m x0, w1
475 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
480 tbz x1, #25, cpu_is_le
481 rev x0, x0 /* BE to LE conversion */
484 ldr x6, =IH_ARCH_DEFAULT
488 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
489 adr x4, secondary_switch_to_el1
490 ldr x5, =ES_TO_AARCH64
493 ldr x5, =ES_TO_AARCH32
495 bl secondary_switch_to_el2
498 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
499 adr x4, secondary_switch_to_el1
503 ldr x5, =ES_TO_AARCH64
504 bl secondary_switch_to_el2
506 ENDPROC(secondary_boot_func)
508 ENTRY(secondary_switch_to_el2)
509 switch_el x6, 1f, 0f, 0f
511 1: armv8_switch_to_el2_m x4, x5, x6
512 ENDPROC(secondary_switch_to_el2)
514 ENTRY(secondary_switch_to_el1)
518 orr x10, x2, x1, lsl #2 /* x10 has LPID */
521 ldr x0, =__spin_table
522 /* physical address of this cpus spin table element */
528 ldr x6, =IH_ARCH_DEFAULT
532 ldr x5, =ES_TO_AARCH32
535 2: ldr x5, =ES_TO_AARCH64
538 switch_el x6, 0f, 1f, 0f
540 1: armv8_switch_to_el1_m x4, x5, x6
541 ENDPROC(secondary_switch_to_el1)
543 /* Ensure that the literals used by the secondary boot code are
544 * assembled within it (this is required so that we can protect
545 * this area with a single memreserve region
549 /* 64 bit alignment for elements accessed as data */
551 .global __real_cntfrq
553 .quad COUNTER_FREQUENCY
554 .globl __secondary_boot_code_size
555 .type __secondary_boot_code_size, %object
556 /* Secondary Boot Code ends here */
557 __secondary_boot_code_size:
558 .quad .-secondary_boot_code