2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/arch/mp.h>
11 #include <asm/arch/soc.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 void *get_spin_tbl_addr(void)
20 phys_addr_t determine_mp_bootpg(void)
22 return (phys_addr_t)&secondary_boot_code;
25 int fsl_layerscape_wake_seconday_cores(void)
27 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
28 #ifdef CONFIG_FSL_LSCH3
29 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
30 #elif defined(CONFIG_FSL_LSCH2)
31 struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
33 u32 cores, cpu_up_mask = 1;
35 u64 *table = get_spin_tbl_addr();
37 #ifdef COUNTER_FREQUENCY_REAL
38 /* update for secondary cores */
39 __real_cntfrq = COUNTER_FREQUENCY_REAL;
40 flush_dcache_range((unsigned long)&__real_cntfrq,
41 (unsigned long)&__real_cntfrq + 8);
45 /* Clear spin table so that secondary processors
46 * observe the correct value after waking up from wfe.
48 memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
49 flush_dcache_range((unsigned long)table,
50 (unsigned long)table +
51 (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
53 printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
55 #ifdef CONFIG_FSL_LSCH3
56 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
57 gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
58 gur_out32(&gur->scratchrw[6], 1);
59 asm volatile("dsb st" : : : "memory");
61 asm volatile("dsb st" : : : "memory");
62 #elif defined(CONFIG_FSL_LSCH2)
63 scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
64 scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
65 asm volatile("dsb st" : : : "memory");
66 gur_out32(&gur->brrl, cores);
67 asm volatile("dsb st" : : : "memory");
69 /* Bootup online cores */
70 scfg_out32(&scfg->corebcr, cores);
72 /* This is needed as a precautionary measure.
73 * If some code before this has accidentally released the secondary
74 * cores then the pre-bootloader code will trap them in a "wfe" unless
75 * the scratchrw[6] is set. In this case we need a sev here to get these
81 flush_dcache_range((unsigned long)table, (unsigned long)table +
82 CONFIG_MAX_CPUS * 64);
83 for (i = 1; i < CONFIG_MAX_CPUS; i++) {
84 if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
85 SPIN_TABLE_ELEM_STATUS_IDX])
86 cpu_up_mask |= 1 << i;
88 if (hweight32(cpu_up_mask) == hweight32(cores))
93 printf("Not all cores (0x%x) are up (0x%x)\n",
97 printf("All (%d) cores are up.\n", hweight32(cores));
102 int is_core_valid(unsigned int core)
104 return !!((1 << core) & cpu_mask());
107 static int is_pos_valid(unsigned int pos)
109 return !!((1 << pos) & cpu_pos_mask());
112 int is_core_online(u64 cpu_id)
115 int pos = id_to_core(cpu_id);
116 table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
117 return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
120 int cpu_reset(int nr)
122 puts("Feature is not implemented.\n");
127 int cpu_disable(int nr)
129 puts("Feature is not implemented.\n");
134 static int core_to_pos(int nr)
136 u32 cores = cpu_pos_mask();
141 } else if (nr >= hweight32(cores)) {
142 puts("Not a valid core number.\n");
146 for (i = 1; i < 32; i++) {
147 if (is_pos_valid(i)) {
160 int cpu_status(int nr)
166 table = (u64 *)get_spin_tbl_addr();
167 printf("table base @ 0x%p\n", table);
169 pos = core_to_pos(nr);
172 table = (u64 *)get_spin_tbl_addr() + pos *
173 WORDS_PER_SPIN_TABLE_ENTRY;
174 printf("table @ 0x%p\n", table);
175 printf(" addr - 0x%016llx\n",
176 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
177 printf(" status - 0x%016llx\n",
178 table[SPIN_TABLE_ELEM_STATUS_IDX]);
179 printf(" lpid - 0x%016llx\n",
180 table[SPIN_TABLE_ELEM_LPID_IDX]);
186 int cpu_release(int nr, int argc, char * const argv[])
189 u64 *table = (u64 *)get_spin_tbl_addr();
192 pos = core_to_pos(nr);
196 table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
197 boot_addr = simple_strtoull(argv[0], NULL, 16);
198 table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
199 flush_dcache_range((unsigned long)table,
200 (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
201 asm volatile("dsb st");
202 smp_kick_all_cpus(); /* only those with entry addr set will run */
204 * When the first release command runs, all cores are set to go. Those
205 * without a valid entry address will be trapped by "wfe". "sev" kicks
206 * them off to check the address again. When set, they continue to run.