2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
14 #include <asm/global_data.h>
15 #include <asm/arch-fsl-layerscape/config.h>
16 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
19 #ifdef CONFIG_SYS_FSL_DDR
20 #include <fsl_ddr_sdram.h>
23 #ifdef CONFIG_CHAIN_OF_TRUST
24 #include <fsl_validate.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 bool soc_has_dp_ddr(void)
31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
32 u32 svr = gur_in32(&gur->svr);
34 /* LS2085A has DP_DDR */
35 if (SVR_SOC_VER(svr) == SVR_LS2085A)
41 bool soc_has_aiop(void)
43 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
44 u32 svr = gur_in32(&gur->svr);
46 /* LS2085A has AIOP */
47 if (SVR_SOC_VER(svr) == SVR_LS2085A)
53 #if defined(CONFIG_FSL_LSCH3)
55 * This erratum requires setting a value to eddrtqcr1 to
56 * optimal the DDR performance.
58 static void erratum_a008336(void)
60 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
63 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
64 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
65 if (fsl_ddr_get_version(0) == 0x50200)
66 out_le32(eddrtqcr1, 0x63b30002);
68 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
69 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
70 if (fsl_ddr_get_version(0) == 0x50200)
71 out_le32(eddrtqcr1, 0x63b30002);
77 * This erratum requires a register write before being Memory
78 * controller 3 being enabled.
80 static void erratum_a008514(void)
82 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
85 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
86 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
87 out_le32(eddrtqcr1, 0x63b20002);
91 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
92 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
94 static unsigned long get_internval_val_mhz(void)
96 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
98 * interval is the number of platform cycles(MHz) between
99 * wake up events generated by EPU.
101 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
104 interval_mhz = simple_strtoul(interval, NULL, 10);
109 void erratum_a009635(void)
112 unsigned long interval_mhz = get_internval_val_mhz();
117 val = in_le32(DCSR_CGACRE5);
118 writel(val | 0x00000200, DCSR_CGACRE5);
120 val = in_le32(EPU_EPCMPR5);
121 writel(interval_mhz, EPU_EPCMPR5);
122 val = in_le32(EPU_EPCCR5);
123 writel(val | 0x82820000, EPU_EPCCR5);
124 val = in_le32(EPU_EPSMCR5);
125 writel(val | 0x002f0000, EPU_EPSMCR5);
126 val = in_le32(EPU_EPECR5);
127 writel(val | 0x20000000, EPU_EPECR5);
128 val = in_le32(EPU_EPGCR);
129 writel(val | 0x80000000, EPU_EPGCR);
131 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
133 static void erratum_rcw_src(void)
135 #if defined(CONFIG_SPL)
136 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
137 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
140 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
141 val &= ~DCFG_PORSR1_RCW_SRC;
142 val |= DCFG_PORSR1_RCW_SRC_NOR;
143 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
147 #define I2C_DEBUG_REG 0x6
148 #define I2C_GLITCH_EN 0x8
150 * This erratum requires setting glitch_en bit to enable
151 * digital glitch filter to improve clock stability.
153 static void erratum_a009203(void)
156 #ifdef CONFIG_SYS_I2C
157 #ifdef I2C1_BASE_ADDR
158 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
160 writeb(I2C_GLITCH_EN, ptr);
162 #ifdef I2C2_BASE_ADDR
163 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
165 writeb(I2C_GLITCH_EN, ptr);
167 #ifdef I2C3_BASE_ADDR
168 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
170 writeb(I2C_GLITCH_EN, ptr);
172 #ifdef I2C4_BASE_ADDR
173 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
175 writeb(I2C_GLITCH_EN, ptr);
180 void bypass_smmu(void)
183 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
184 out_le32(SMMU_SCR0, val);
185 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
186 out_le32(SMMU_NSCR0, val);
188 void fsl_lsch3_early_init_f(void)
191 init_early_memctl_regs(); /* tighten IFC timing */
195 #ifdef CONFIG_CHAIN_OF_TRUST
196 /* In case of Secure Boot, the IBR configures the SMMU
197 * to allow only Secure transactions.
198 * SMMU must be reset in bypass mode.
199 * Set the ClientPD bit and Clear the USFCFG Bit
201 if (fsl_check_boot_mode_secure() == 1)
206 #ifdef CONFIG_SCSI_AHCI_PLAT
209 struct ccsr_ahci __iomem *ccsr_ahci;
211 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
212 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
213 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
215 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
216 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
217 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
219 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
226 #elif defined(CONFIG_FSL_LSCH2)
227 #ifdef CONFIG_SCSI_AHCI_PLAT
230 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
232 #ifdef CONFIG_ARCH_LS1046A
233 /* Disable SATA ECC */
234 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
236 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
237 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
238 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
240 ahci_init((void __iomem *)CONFIG_SYS_SATA);
247 static void erratum_a009929(void)
249 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
250 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
251 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
252 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
254 rstrqmr1 |= 0x00000400;
255 gur_out32(&gur->rstrqmr1, rstrqmr1);
256 writel(0x01000000, dcsr_cop_ccp);
261 * This erratum requires setting a value to eddrtqcr1 to optimal
262 * the DDR performance. The eddrtqcr1 register is in SCFG space
263 * of LS1043A and the offset is 0x157_020c.
265 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
266 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
267 #error A009660 and A008514 can not be both enabled.
270 static void erratum_a009660(void)
272 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
273 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
274 out_be32(eddrtqcr1, 0x63b20042);
278 static void erratum_a008850_early(void)
280 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
282 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
283 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
285 /* disables propagation of barrier transactions to DDRC from CCI400 */
286 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
288 /* disable the re-ordering in DDRC */
289 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
293 void erratum_a008850_post(void)
295 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
297 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
298 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
301 /* enable propagation of barrier transactions to DDRC from CCI400 */
302 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
304 /* enable the re-ordering in DDRC */
305 tmp = ddr_in32(&ddr->eor);
306 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
307 ddr_out32(&ddr->eor, tmp);
311 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
312 void erratum_a010315(void)
316 for (i = PCIE1; i <= PCIE4; i++)
317 if (!is_serdes_configured(i)) {
318 debug("PCIe%d: disabled all R/W permission!\n", i);
319 set_pcie_ns_access(i, 0);
324 static void erratum_a010539(void)
326 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
327 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
330 porsr1 = in_be32(&gur->porsr1);
331 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
332 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
337 void fsl_lsch2_early_init_f(void)
339 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
340 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
342 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
343 enable_layerscape_ns_access();
346 #ifdef CONFIG_FSL_IFC
347 init_early_memctl_regs(); /* tighten IFC timing */
350 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
351 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
353 /* Make SEC reads and writes snoopable */
354 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
355 SCFG_SNPCNFGCR_SECWRSNP |
356 SCFG_SNPCNFGCR_SATARDSNP |
357 SCFG_SNPCNFGCR_SATAWRSNP);
360 * Enable snoop requests and DVM message requests for
361 * Slave insterface S4 (A53 core cluster)
363 out_le32(&cci->slave[4].snoop_ctrl,
364 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
367 erratum_a008850_early(); /* part 1 of 2 */
374 #ifdef CONFIG_BOARD_LATE_INIT
375 int board_late_init(void)
377 #ifdef CONFIG_SCSI_AHCI_PLAT
380 #ifdef CONFIG_CHAIN_OF_TRUST
381 fsl_setenv_chain_of_trust();