2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
14 #include <asm/global_data.h>
15 #include <asm/arch-fsl-layerscape/config.h>
16 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
19 #ifdef CONFIG_SYS_FSL_DDR
20 #include <fsl_ddr_sdram.h>
23 #ifdef CONFIG_CHAIN_OF_TRUST
24 #include <fsl_validate.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 bool soc_has_dp_ddr(void)
31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
32 u32 svr = gur_in32(&gur->svr);
34 /* LS2085A has DP_DDR */
35 if (SVR_SOC_VER(svr) == SVR_LS2085A)
41 bool soc_has_aiop(void)
43 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
44 u32 svr = gur_in32(&gur->svr);
46 /* LS2085A has AIOP */
47 if (SVR_SOC_VER(svr) == SVR_LS2085A)
55 * This erratum requires setting a value to eddrtqcr1 to
56 * optimal the DDR performance.
58 static void erratum_a008336(void)
62 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
63 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
64 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
65 if (fsl_ddr_get_version(0) == 0x50200)
66 out_le32(eddrtqcr1, 0x63b30002);
68 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
69 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
70 if (fsl_ddr_get_version(0) == 0x50200)
71 out_le32(eddrtqcr1, 0x63b30002);
77 * This erratum requires a register write before being Memory
78 * controller 3 being enabled.
80 static void erratum_a008514(void)
84 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
85 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
86 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
87 out_le32(eddrtqcr1, 0x63b20002);
91 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
92 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
94 static unsigned long get_internval_val_mhz(void)
96 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
98 * interval is the number of platform cycles(MHz) between
99 * wake up events generated by EPU.
101 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
104 interval_mhz = simple_strtoul(interval, NULL, 10);
109 void erratum_a009635(void)
112 unsigned long interval_mhz = get_internval_val_mhz();
117 val = in_le32(DCSR_CGACRE5);
118 writel(val | 0x00000200, DCSR_CGACRE5);
120 val = in_le32(EPU_EPCMPR5);
121 writel(interval_mhz, EPU_EPCMPR5);
122 val = in_le32(EPU_EPCCR5);
123 writel(val | 0x82820000, EPU_EPCCR5);
124 val = in_le32(EPU_EPSMCR5);
125 writel(val | 0x002f0000, EPU_EPSMCR5);
126 val = in_le32(EPU_EPECR5);
127 writel(val | 0x20000000, EPU_EPECR5);
128 val = in_le32(EPU_EPGCR);
129 writel(val | 0x80000000, EPU_EPGCR);
131 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
133 static void erratum_rcw_src(void)
135 #if defined(CONFIG_SPL)
136 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
137 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
140 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
141 val &= ~DCFG_PORSR1_RCW_SRC;
142 val |= DCFG_PORSR1_RCW_SRC_NOR;
143 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
147 #define I2C_DEBUG_REG 0x6
148 #define I2C_GLITCH_EN 0x8
150 * This erratum requires setting glitch_en bit to enable
151 * digital glitch filter to improve clock stability.
153 static void erratum_a009203(void)
156 #ifdef CONFIG_SYS_I2C
157 #ifdef I2C1_BASE_ADDR
158 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
160 writeb(I2C_GLITCH_EN, ptr);
162 #ifdef I2C2_BASE_ADDR
163 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
165 writeb(I2C_GLITCH_EN, ptr);
167 #ifdef I2C3_BASE_ADDR
168 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
170 writeb(I2C_GLITCH_EN, ptr);
172 #ifdef I2C4_BASE_ADDR
173 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
175 writeb(I2C_GLITCH_EN, ptr);
179 void bypass_smmu(void)
182 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
183 out_le32(SMMU_SCR0, val);
184 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
185 out_le32(SMMU_NSCR0, val);
187 void fsl_lsch3_early_init_f(void)
190 init_early_memctl_regs(); /* tighten IFC timing */
194 #ifdef CONFIG_CHAIN_OF_TRUST
195 /* In case of Secure Boot, the IBR configures the SMMU
196 * to allow only Secure transactions.
197 * SMMU must be reset in bypass mode.
198 * Set the ClientPD bit and Clear the USFCFG Bit
200 if (fsl_check_boot_mode_secure() == 1)
205 #ifdef CONFIG_SCSI_AHCI_PLAT
208 struct ccsr_ahci __iomem *ccsr_ahci;
210 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
211 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
212 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
214 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
215 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
216 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
218 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
225 #elif defined(CONFIG_FSL_LSCH2)
226 #ifdef CONFIG_SCSI_AHCI_PLAT
229 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
231 #ifdef CONFIG_ARCH_LS1046A
232 /* Disable SATA ECC */
233 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
235 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
236 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
237 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
239 ahci_init((void __iomem *)CONFIG_SYS_SATA);
246 static void erratum_a009929(void)
248 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
249 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
250 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
251 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
253 rstrqmr1 |= 0x00000400;
254 gur_out32(&gur->rstrqmr1, rstrqmr1);
255 writel(0x01000000, dcsr_cop_ccp);
260 * This erratum requires setting a value to eddrtqcr1 to optimal
261 * the DDR performance. The eddrtqcr1 register is in SCFG space
262 * of LS1043A and the offset is 0x157_020c.
264 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
265 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
266 #error A009660 and A008514 can not be both enabled.
269 static void erratum_a009660(void)
271 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
272 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
273 out_be32(eddrtqcr1, 0x63b20042);
277 static void erratum_a008850_early(void)
279 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
281 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
282 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
284 /* disables propagation of barrier transactions to DDRC from CCI400 */
285 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
287 /* disable the re-ordering in DDRC */
288 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
292 void erratum_a008850_post(void)
294 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
296 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
297 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
300 /* enable propagation of barrier transactions to DDRC from CCI400 */
301 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
303 /* enable the re-ordering in DDRC */
304 tmp = ddr_in32(&ddr->eor);
305 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
306 ddr_out32(&ddr->eor, tmp);
310 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
311 void erratum_a010315(void)
315 for (i = PCIE1; i <= PCIE4; i++)
316 if (!is_serdes_configured(i)) {
317 debug("PCIe%d: disabled all R/W permission!\n", i);
318 set_pcie_ns_access(i, 0);
323 static void erratum_a010539(void)
325 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
326 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
329 porsr1 = in_be32(&gur->porsr1);
330 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
331 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
336 void fsl_lsch2_early_init_f(void)
338 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
339 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
341 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
342 enable_layerscape_ns_access();
345 #ifdef CONFIG_FSL_IFC
346 init_early_memctl_regs(); /* tighten IFC timing */
349 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
350 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
352 /* Make SEC reads and writes snoopable */
353 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
354 SCFG_SNPCNFGCR_SECWRSNP |
355 SCFG_SNPCNFGCR_SATARDSNP |
356 SCFG_SNPCNFGCR_SATAWRSNP);
359 * Enable snoop requests and DVM message requests for
360 * Slave insterface S4 (A53 core cluster)
362 out_le32(&cci->slave[4].snoop_ctrl,
363 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
366 erratum_a008850_early(); /* part 1 of 2 */
373 #ifdef CONFIG_BOARD_LATE_INIT
374 int board_late_init(void)
376 #ifdef CONFIG_SCSI_AHCI_PLAT
379 #ifdef CONFIG_CHAIN_OF_TRUST
380 fsl_setenv_chain_of_trust();