2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/soc.h>
11 #include <asm/global_data.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
16 static void erratum_a008751(void)
18 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
19 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
21 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
25 static void erratum_rcw_src(void)
27 #if defined(CONFIG_SPL)
28 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
29 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
32 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
33 val &= ~DCFG_PORSR1_RCW_SRC;
34 val |= DCFG_PORSR1_RCW_SRC_NOR;
35 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
39 #define I2C_DEBUG_REG 0x6
40 #define I2C_GLITCH_EN 0x8
42 * This erratum requires setting glitch_en bit to enable
43 * digital glitch filter to improve clock stability.
45 static void erratum_a009203(void)
50 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
52 writeb(I2C_GLITCH_EN, ptr);
55 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
57 writeb(I2C_GLITCH_EN, ptr);
60 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
62 writeb(I2C_GLITCH_EN, ptr);
65 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
67 writeb(I2C_GLITCH_EN, ptr);
72 void fsl_lsch3_early_init_f(void)
76 init_early_memctl_regs(); /* tighten IFC timing */
80 #elif defined(CONFIG_LS1043A)
81 void fsl_lsch2_early_init_f(void)
83 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
86 init_early_memctl_regs(); /* tighten IFC timing */
90 * Enable snoop requests and DVM message requests for
91 * Slave insterface S4 (A53 core cluster)
93 out_le32(&cci->slave[4].snoop_ctrl,
94 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
98 #ifdef CONFIG_BOARD_LATE_INIT
99 int board_late_init(void)