2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/soc.h>
13 #include <asm/global_data.h>
14 #include <asm/arch-fsl-layerscape/config.h>
15 #ifdef CONFIG_SYS_FSL_DDR
16 #include <fsl_ddr_sdram.h>
19 #ifdef CONFIG_CHAIN_OF_TRUST
20 #include <fsl_validate.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 bool soc_has_dp_ddr(void)
27 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
28 u32 svr = gur_in32(&gur->svr);
30 /* LS2085A has DP_DDR */
31 if (SVR_SOC_VER(svr) == SVR_LS2085A)
37 bool soc_has_aiop(void)
39 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
40 u32 svr = gur_in32(&gur->svr);
42 /* LS2085A has AIOP */
43 if (SVR_SOC_VER(svr) == SVR_LS2085A)
51 * This erratum requires setting a value to eddrtqcr1 to
52 * optimal the DDR performance.
54 static void erratum_a008336(void)
58 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
59 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
60 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
61 out_le32(eddrtqcr1, 0x63b30002);
63 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
64 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
65 out_le32(eddrtqcr1, 0x63b30002);
71 * This erratum requires a register write before being Memory
72 * controller 3 being enabled.
74 static void erratum_a008514(void)
78 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
79 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
80 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
81 out_le32(eddrtqcr1, 0x63b20002);
85 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
86 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
88 static unsigned long get_internval_val_mhz(void)
90 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
92 * interval is the number of platform cycles(MHz) between
93 * wake up events generated by EPU.
95 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
98 interval_mhz = simple_strtoul(interval, NULL, 10);
103 void erratum_a009635(void)
106 unsigned long interval_mhz = get_internval_val_mhz();
111 val = in_le32(DCSR_CGACRE5);
112 writel(val | 0x00000200, DCSR_CGACRE5);
114 val = in_le32(EPU_EPCMPR5);
115 writel(interval_mhz, EPU_EPCMPR5);
116 val = in_le32(EPU_EPCCR5);
117 writel(val | 0x82820000, EPU_EPCCR5);
118 val = in_le32(EPU_EPSMCR5);
119 writel(val | 0x002f0000, EPU_EPSMCR5);
120 val = in_le32(EPU_EPECR5);
121 writel(val | 0x20000000, EPU_EPECR5);
122 val = in_le32(EPU_EPGCR);
123 writel(val | 0x80000000, EPU_EPGCR);
125 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
127 static void erratum_rcw_src(void)
129 #if defined(CONFIG_SPL)
130 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
131 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
134 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
135 val &= ~DCFG_PORSR1_RCW_SRC;
136 val |= DCFG_PORSR1_RCW_SRC_NOR;
137 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
141 #define I2C_DEBUG_REG 0x6
142 #define I2C_GLITCH_EN 0x8
144 * This erratum requires setting glitch_en bit to enable
145 * digital glitch filter to improve clock stability.
147 static void erratum_a009203(void)
150 #ifdef CONFIG_SYS_I2C
151 #ifdef I2C1_BASE_ADDR
152 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
154 writeb(I2C_GLITCH_EN, ptr);
156 #ifdef I2C2_BASE_ADDR
157 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
159 writeb(I2C_GLITCH_EN, ptr);
161 #ifdef I2C3_BASE_ADDR
162 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
164 writeb(I2C_GLITCH_EN, ptr);
166 #ifdef I2C4_BASE_ADDR
167 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
169 writeb(I2C_GLITCH_EN, ptr);
173 void bypass_smmu(void)
176 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
177 out_le32(SMMU_SCR0, val);
178 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
179 out_le32(SMMU_NSCR0, val);
181 void fsl_lsch3_early_init_f(void)
184 init_early_memctl_regs(); /* tighten IFC timing */
188 #ifdef CONFIG_CHAIN_OF_TRUST
189 /* In case of Secure Boot, the IBR configures the SMMU
190 * to allow only Secure transactions.
191 * SMMU must be reset in bypass mode.
192 * Set the ClientPD bit and Clear the USFCFG Bit
194 if (fsl_check_boot_mode_secure() == 1)
199 #ifdef CONFIG_SCSI_AHCI_PLAT
202 struct ccsr_ahci __iomem *ccsr_ahci;
204 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
205 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
206 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
208 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
209 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
210 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
212 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
219 #elif defined(CONFIG_FSL_LSCH2)
220 #ifdef CONFIG_SCSI_AHCI_PLAT
223 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
225 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
226 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
227 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
228 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
230 ahci_init((void __iomem *)CONFIG_SYS_SATA);
237 static void erratum_a009929(void)
239 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
240 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
241 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
242 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
244 rstrqmr1 |= 0x00000400;
245 gur_out32(&gur->rstrqmr1, rstrqmr1);
246 writel(0x01000000, dcsr_cop_ccp);
251 * This erratum requires setting a value to eddrtqcr1 to optimal
252 * the DDR performance. The eddrtqcr1 register is in SCFG space
253 * of LS1043A and the offset is 0x157_020c.
255 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
256 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
257 #error A009660 and A008514 can not be both enabled.
260 static void erratum_a009660(void)
262 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
263 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
264 out_be32(eddrtqcr1, 0x63b20042);
268 static void erratum_a008850_early(void)
270 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
272 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
273 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
275 /* disables propagation of barrier transactions to DDRC from CCI400 */
276 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
278 /* disable the re-ordering in DDRC */
279 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
283 void erratum_a008850_post(void)
285 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
287 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
288 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
291 /* enable propagation of barrier transactions to DDRC from CCI400 */
292 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
294 /* enable the re-ordering in DDRC */
295 tmp = ddr_in32(&ddr->eor);
296 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
297 ddr_out32(&ddr->eor, tmp);
301 void fsl_lsch2_early_init_f(void)
303 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
304 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
306 #ifdef CONFIG_FSL_IFC
307 init_early_memctl_regs(); /* tighten IFC timing */
310 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
311 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
313 /* Make SEC reads and writes snoopable */
314 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
315 SCFG_SNPCNFGCR_SECWRSNP);
318 * Enable snoop requests and DVM message requests for
319 * Slave insterface S4 (A53 core cluster)
321 out_le32(&cci->slave[4].snoop_ctrl,
322 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
325 erratum_a008850_early(); /* part 1 of 2 */
331 #ifdef CONFIG_BOARD_LATE_INIT
332 int board_late_init(void)
334 #ifdef CONFIG_SCSI_AHCI_PLAT
337 #ifdef CONFIG_CHAIN_OF_TRUST
338 fsl_setenv_chain_of_trust();