2 * (C) Copyright 2014-2016, Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/armv8/mmu.h>
12 #include <asm/arch/mc_me_regs.h>
15 DECLARE_GLOBAL_DATA_PTR;
19 return readl(MC_ME_CS);
22 #ifndef CONFIG_SYS_DCACHE_OFF
24 #define S32V234_IRAM_BASE 0x3e800000UL
25 #define S32V234_IRAM_SIZE 0x800000UL
26 #define S32V234_DRAM_BASE1 0x80000000UL
27 #define S32V234_DRAM_SIZE1 0x40000000UL
28 #define S32V234_DRAM_BASE2 0xC0000000UL
29 #define S32V234_DRAM_SIZE2 0x20000000UL
30 #define S32V234_PERIPH_BASE 0x40000000UL
31 #define S32V234_PERIPH_SIZE 0x40000000UL
33 static struct mm_region s32v234_mem_map[] = {
35 .base = S32V234_IRAM_BASE,
36 .size = S32V234_IRAM_SIZE,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
40 .base = S32V234_DRAM_BASE1,
41 .size = S32V234_DRAM_SIZE1,
42 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 .base = S32V234_PERIPH_BASE,
46 .size = S32V234_PERIPH_SIZE,
47 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
49 /* TODO: Do we need these? */
50 /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */
52 .base = S32V234_DRAM_BASE2,
53 .size = S32V234_DRAM_SIZE2,
54 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
62 struct mm_region *mem_map = s32v234_mem_map;
67 * Return the number of cores on this SOC.
69 int cpu_numcores(void)
75 numcores = hweight32(cpu_mask());
77 /* Verify if M4 is deactivated */
84 #if defined(CONFIG_ARCH_EARLY_INIT_R)
85 int arch_early_init_r(void)
88 asm volatile ("dsb sy");
89 rv = fsl_s32v234_wake_seconday_cores();
92 printf("Did not wake secondary cores\n");
97 #endif /* CONFIG_ARCH_EARLY_INIT_R */