2 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/mc_cgm_regs.h>
12 #include <asm/arch/mc_me_regs.h>
13 #include <asm/arch/mc_rgm_regs.h>
20 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
21 u32 cpu = readl(&mscmir->cpxtype);
26 DECLARE_GLOBAL_DATA_PTR;
28 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
29 u32 pllfd, u32 selected_output)
31 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
32 u32 plldv_rfdphi_div = 0, fout = 0;
33 u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
35 if (selected_output > DFS_MAXNUMBER) {
40 (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
41 plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
43 pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
45 plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
47 /* The formula for VCO is from TR manual, rev. D */
48 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
50 if (selected_output != 0) {
51 /* Determine the RFDPHI for PHI1 */
53 (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
54 PLLDIG_PLLDV_RFDPHI1_OFFSET;
55 plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
56 if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
58 readl(DFS_DVPORTn(pll, selected_output - 1));
60 (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
61 DFS_DVPORTn_MFI_OFFSET;
63 (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
64 DFS_DVPORTn_MFI_OFFSET;
65 fout = vco / (dfs_mfi + (dfs_mfn / 256));
67 fout = vco / plldv_rfdphi_div;
71 /* Determine the RFDPHI for PHI0 */
73 (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
74 PLLDIG_PLLDV_RFDPHI_OFFSET;
75 fout = vco / plldv_rfdphi_div;
82 /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
83 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
88 plldv = readl(PLLDIG_PLLDV(pll));
89 pllfd = readl(PLLDIG_PLLFD(pll));
91 return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
94 static u32 get_mcu_main_clk(void)
100 sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
101 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
104 readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
105 coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
108 switch (sysclk_sel) {
109 case MC_CGM_SC_SEL_FIRC:
110 freq = FIRC_CLK_FREQ;
112 case MC_CGM_SC_SEL_XOSC:
113 freq = XOSC_CLK_FREQ;
115 case MC_CGM_SC_SEL_ARMPLL:
116 /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
117 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
119 case MC_CGM_SC_SEL_CLKDISABLE:
120 printf("Sysclk is disabled\n");
123 printf("unsupported system clock select\n");
126 return freq / coreclk_div;
129 static u32 get_sys_clk(u32 number)
131 u32 sysclk_div, sysclk_div_number;
137 sysclk_div_number = 0;
140 sysclk_div_number = 1;
143 printf("unsupported system clock \n");
146 sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
147 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
150 readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
151 MC_CGM_SC_DCn_PREDIV_MASK;
152 sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
155 switch (sysclk_sel) {
156 case MC_CGM_SC_SEL_FIRC:
157 freq = FIRC_CLK_FREQ;
159 case MC_CGM_SC_SEL_XOSC:
160 freq = XOSC_CLK_FREQ;
162 case MC_CGM_SC_SEL_ARMPLL:
163 /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
164 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
166 case MC_CGM_SC_SEL_CLKDISABLE:
167 printf("Sysclk is disabled\n");
170 printf("unsupported system clock select\n");
173 return freq / sysclk_div;
176 static u32 get_peripherals_clk(void)
182 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
183 MC_CGM_ACn_DCm_PREDIV_MASK;
184 aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
187 freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
189 return freq / aux5clk_div;
193 static u32 get_uart_clk(void)
195 u32 auxclk3_div, auxclk3_sel, freq = 0;
198 readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
199 auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
202 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
203 MC_CGM_ACn_DCm_PREDIV_MASK;
204 auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
207 switch (auxclk3_sel) {
208 case MC_CGM_ACn_SEL_FIRC:
209 freq = FIRC_CLK_FREQ;
211 case MC_CGM_ACn_SEL_XOSC:
212 freq = XOSC_CLK_FREQ;
214 case MC_CGM_ACn_SEL_PERPLLDIVX:
215 freq = get_peripherals_clk() / 3;
217 case MC_CGM_ACn_SEL_SYSCLK:
218 freq = get_sys_clk(6);
221 printf("unsupported system clock select\n");
224 return freq / auxclk3_div;
227 static u32 get_fec_clk(void)
233 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
234 MC_CGM_ACn_DCm_PREDIV_MASK;
235 aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
238 freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
240 return freq / aux2clk_div;
243 static u32 get_usdhc_clk(void)
249 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
250 MC_CGM_ACn_DCm_PREDIV_MASK;
251 aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
254 freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
256 return freq / aux15clk_div;
259 static u32 get_i2c_clk(void)
261 return get_peripherals_clk();
264 /* return clocks in Hz */
265 unsigned int mxc_get_clock(enum mxc_clock clk)
269 return get_mcu_main_clk();
270 case MXC_PERIPHERALS_CLK:
271 return get_peripherals_clk();
273 return get_uart_clk();
275 return get_fec_clk();
277 return get_i2c_clk();
279 return get_usdhc_clk();
283 printf("Error: Unsupported function to read the frequency! \
284 Please define it correctly!");
288 /* Not yet implemented - int soc_clk_dump(); */
290 #if defined(CONFIG_DISPLAY_CPUINFO)
291 static char *get_reset_cause(void)
293 u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
301 return "FCCU soft reaction";
303 return "FCCU hard reaction";
305 return "Software Functional reset";
307 return "Self Test done reset";
309 return "External reset";
311 return "unknown reset";
316 #define SRC_SCR_SW_RST (1<<12)
318 void reset_cpu(ulong addr)
320 printf("Feature not supported.\n");
323 int print_cpuinfo(void)
325 printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
326 mxc_get_clock(MXC_ARM_CLK) / 1000000);
327 printf("Reset cause: %s\n", get_reset_cause());
333 int cpu_eth_init(bd_t * bis)
337 #if defined(CONFIG_FEC_MXC)
338 rc = fecmxc_initialize(bis);
346 #ifdef CONFIG_FSL_ESDHC
347 gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);