1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
8 #include <asm/arch/imx-regs.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/mc_cgm_regs.h>
11 #include <asm/arch/mc_me_regs.h>
12 #include <asm/arch/mc_rgm_regs.h>
19 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
20 u32 cpu = readl(&mscmir->cpxtype);
25 DECLARE_GLOBAL_DATA_PTR;
27 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
28 u32 pllfd, u32 selected_output)
30 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
31 u32 plldv_rfdphi_div = 0, fout = 0;
32 u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
34 if (selected_output > DFS_MAXNUMBER) {
39 (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
40 plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
42 pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
44 plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
46 /* The formula for VCO is from TR manual, rev. D */
47 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
49 if (selected_output != 0) {
50 /* Determine the RFDPHI for PHI1 */
52 (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
53 PLLDIG_PLLDV_RFDPHI1_OFFSET;
54 plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
55 if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
57 readl(DFS_DVPORTn(pll, selected_output - 1));
59 (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
60 DFS_DVPORTn_MFI_OFFSET;
62 (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
63 DFS_DVPORTn_MFI_OFFSET;
64 fout = vco / (dfs_mfi + (dfs_mfn / 256));
66 fout = vco / plldv_rfdphi_div;
70 /* Determine the RFDPHI for PHI0 */
72 (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
73 PLLDIG_PLLDV_RFDPHI_OFFSET;
74 fout = vco / plldv_rfdphi_div;
81 /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
82 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
87 plldv = readl(PLLDIG_PLLDV(pll));
88 pllfd = readl(PLLDIG_PLLFD(pll));
90 return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
93 static u32 get_mcu_main_clk(void)
99 sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
100 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
103 readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
104 coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
107 switch (sysclk_sel) {
108 case MC_CGM_SC_SEL_FIRC:
109 freq = FIRC_CLK_FREQ;
111 case MC_CGM_SC_SEL_XOSC:
112 freq = XOSC_CLK_FREQ;
114 case MC_CGM_SC_SEL_ARMPLL:
115 /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
116 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
118 case MC_CGM_SC_SEL_CLKDISABLE:
119 printf("Sysclk is disabled\n");
122 printf("unsupported system clock select\n");
125 return freq / coreclk_div;
128 static u32 get_sys_clk(u32 number)
130 u32 sysclk_div, sysclk_div_number;
136 sysclk_div_number = 0;
139 sysclk_div_number = 1;
142 printf("unsupported system clock \n");
145 sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
146 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
149 readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
150 MC_CGM_SC_DCn_PREDIV_MASK;
151 sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
154 switch (sysclk_sel) {
155 case MC_CGM_SC_SEL_FIRC:
156 freq = FIRC_CLK_FREQ;
158 case MC_CGM_SC_SEL_XOSC:
159 freq = XOSC_CLK_FREQ;
161 case MC_CGM_SC_SEL_ARMPLL:
162 /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
163 freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
165 case MC_CGM_SC_SEL_CLKDISABLE:
166 printf("Sysclk is disabled\n");
169 printf("unsupported system clock select\n");
172 return freq / sysclk_div;
175 static u32 get_peripherals_clk(void)
181 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
182 MC_CGM_ACn_DCm_PREDIV_MASK;
183 aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
186 freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
188 return freq / aux5clk_div;
192 static u32 get_uart_clk(void)
194 u32 auxclk3_div, auxclk3_sel, freq = 0;
197 readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
198 auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
201 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
202 MC_CGM_ACn_DCm_PREDIV_MASK;
203 auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
206 switch (auxclk3_sel) {
207 case MC_CGM_ACn_SEL_FIRC:
208 freq = FIRC_CLK_FREQ;
210 case MC_CGM_ACn_SEL_XOSC:
211 freq = XOSC_CLK_FREQ;
213 case MC_CGM_ACn_SEL_PERPLLDIVX:
214 freq = get_peripherals_clk() / 3;
216 case MC_CGM_ACn_SEL_SYSCLK:
217 freq = get_sys_clk(6);
220 printf("unsupported system clock select\n");
223 return freq / auxclk3_div;
226 static u32 get_fec_clk(void)
232 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
233 MC_CGM_ACn_DCm_PREDIV_MASK;
234 aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
237 freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
239 return freq / aux2clk_div;
242 static u32 get_usdhc_clk(void)
248 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
249 MC_CGM_ACn_DCm_PREDIV_MASK;
250 aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
253 freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
255 return freq / aux15clk_div;
258 static u32 get_i2c_clk(void)
260 return get_peripherals_clk();
263 /* return clocks in Hz */
264 unsigned int mxc_get_clock(enum mxc_clock clk)
268 return get_mcu_main_clk();
269 case MXC_PERIPHERALS_CLK:
270 return get_peripherals_clk();
272 return get_uart_clk();
274 return get_fec_clk();
276 return get_i2c_clk();
278 return get_usdhc_clk();
282 printf("Error: Unsupported function to read the frequency! \
283 Please define it correctly!");
287 /* Not yet implemented - int soc_clk_dump(); */
289 #if defined(CONFIG_DISPLAY_CPUINFO)
290 static char *get_reset_cause(void)
292 u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
300 return "FCCU soft reaction";
302 return "FCCU hard reaction";
304 return "Software Functional reset";
306 return "Self Test done reset";
308 return "External reset";
310 return "unknown reset";
315 #define SRC_SCR_SW_RST (1<<12)
317 void reset_cpu(ulong addr)
319 printf("Feature not supported.\n");
322 int print_cpuinfo(void)
324 printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
325 mxc_get_clock(MXC_ARM_CLK) / 1000000);
326 printf("Reset cause: %s\n", get_reset_cause());
332 int cpu_eth_init(bd_t * bis)
336 #if defined(CONFIG_FEC_MXC)
337 rc = fecmxc_initialize(bis);
345 #ifdef CONFIG_FSL_ESDHC
346 gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);