]> git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv8/smccc-call.S
arm64: zynqmp: Wire SD1 level shifter mode to SPL
[u-boot] / arch / arm / cpu / armv8 / smccc-call.S
1 /*
2  * Copyright (c) 2015, Linaro Limited
3  *
4  * SPDX-License-Identifier:     GPL-2.0
5  */
6 #include <linux/linkage.h>
7 #include <linux/arm-smccc.h>
8 #include <generated/asm-offsets.h>
9
10         .macro SMCCC instr
11         .cfi_startproc
12         \instr  #0
13         ldr     x4, [sp]
14         stp     x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
15         stp     x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
16         ldr     x4, [sp, #8]
17         cbz     x4, 1f /* no quirk structure */
18         ldr     x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
19         cmp     x9, #ARM_SMCCC_QUIRK_QCOM_A6
20         b.ne    1f
21         str     x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
22 1:      ret
23         .cfi_endproc
24         .endm
25
26 /*
27  * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
28  *                unsigned long a3, unsigned long a4, unsigned long a5,
29  *                unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
30  *                struct arm_smccc_quirk *quirk)
31  */
32 ENTRY(__arm_smccc_smc)
33         SMCCC   smc
34 ENDPROC(__arm_smccc_smc)
35
36 /*
37  * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
38  *                unsigned long a3, unsigned long a4, unsigned long a5,
39  *                unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
40  *                struct arm_smccc_quirk *quirk)
41  */
42 ENTRY(__arm_smccc_hvc)
43         SMCCC   hvc
44 ENDPROC(__arm_smccc_hvc)