3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
24 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
26 * Various SoCs need something special and SoC-specific up front in
27 * order to boot, allow them to set that in their boot0.h file and then
30 #include <asm/arch/boot0.h>
38 .quad CONFIG_SYS_TEXT_BASE
41 * These are defined in the linker script.
49 .quad __bss_start - _start
53 .quad __bss_end - _start
56 /* Allow the board to save important registers */
58 .globl save_boot_params_ret
61 #ifdef CONFIG_SYS_RESET_SCTRL
65 * Could be EL3/EL2/EL1, Initial State:
66 * Little Endian, MMU Disabled, i/dCache Disabled
69 switch_el x1, 3f, 2f, 1f
72 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
74 msr cptr_el3, xzr /* Enable FP/SIMD */
75 #ifdef COUNTER_FREQUENCY
76 ldr x0, =COUNTER_FREQUENCY
77 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
82 msr cptr_el2, x0 /* Enable FP/SIMD */
86 msr cpacr_el1, x0 /* Enable FP/SIMD */
89 /* Apply ARM core specific erratas */
93 * Cache/BPB/TLB Invalidate
94 * i-cache is invalidated before enabled in icache_enable()
95 * tlb is invalidated before mmu is enabled in dcache_enable()
96 * d-cache is invalidated before enabled in dcache_enable()
99 /* Processor specific initialization */
102 #if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
103 branch_if_master x0, x1, master_cpu
104 b spin_table_secondary_jump
106 #elif defined(CONFIG_ARMV8_MULTIENTRY)
107 branch_if_master x0, x1, master_cpu
114 ldr x1, =CPU_RELEASE_ADDR
117 br x0 /* branch to the given address */
118 #endif /* CONFIG_ARMV8_MULTIENTRY */
122 #ifdef CONFIG_SYS_RESET_SCTRL
124 switch_el x1, 3f, 2f, 1f
138 switch_el x1, 6f, 5f, 4f
151 b __asm_invalidate_tlb_all
155 /*-----------------------------------------------------------------------*/
157 WEAK(apply_core_errata)
159 mov x29, lr /* Save LR */
160 /* For now, we support Cortex-A57 specific errata only */
162 /* Check if we are running on a Cortex-A57 core */
163 branch_if_a57_core x0, apply_a57_core_errata
165 mov lr, x29 /* Restore LR */
168 apply_a57_core_errata:
170 #ifdef CONFIG_ARM_ERRATA_828024
171 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
172 /* Disable non-allocate hint of w-b-n-a memory type */
174 /* Disable write streaming no L1-allocate threshold */
176 /* Disable write streaming no-allocate threshold */
178 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
181 #ifdef CONFIG_ARM_ERRATA_826974
182 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
183 /* Disable speculative load execution ahead of a DMB */
185 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
188 #ifdef CONFIG_ARM_ERRATA_833471
189 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
190 /* FPSCR write flush.
191 * Note that in some cases where a flush is unnecessary this
192 could impact performance. */
194 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
197 #ifdef CONFIG_ARM_ERRATA_829520
198 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
199 /* Disable Indirect Predictor bit will prevent this erratum
201 * Note that in some cases where a flush is unnecessary this
202 could impact performance. */
204 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
207 #ifdef CONFIG_ARM_ERRATA_833069
208 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
209 /* Disable Enable Invalidates of BTB bit */
211 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
214 ENDPROC(apply_core_errata)
216 /*-----------------------------------------------------------------------*/
219 mov x29, lr /* Save LR */
221 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
222 branch_if_slave x0, 1f
226 #if defined(CONFIG_GICV3)
228 bl gic_init_secure_percpu
229 #elif defined(CONFIG_GICV2)
232 bl gic_init_secure_percpu
236 #ifdef CONFIG_ARMV8_MULTIENTRY
237 branch_if_master x0, x1, 2f
240 * Slave should wait for master clearing spin table.
241 * This sync prevent salves observing incorrect
242 * value of spin table and jumping to wrong place.
244 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
248 bl gic_wait_for_interrupt
252 * All slaves will enter EL2 and optionally EL1.
254 bl armv8_switch_to_el2
255 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
256 bl armv8_switch_to_el1
259 #endif /* CONFIG_ARMV8_MULTIENTRY */
262 mov lr, x29 /* Restore LR */
264 ENDPROC(lowlevel_init)
266 WEAK(smp_kick_all_cpus)
267 /* Kick secondary cpus up by SGI 0 interrupt */
268 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
270 b gic_kick_secondary_cpus
273 ENDPROC(smp_kick_all_cpus)
275 /*-----------------------------------------------------------------------*/
277 ENTRY(c_runtime_cpu_setup)
280 switch_el x1, 3f, 2f, 1f
289 ENDPROC(c_runtime_cpu_setup)
291 WEAK(save_boot_params)
292 b save_boot_params_ret /* back to my caller */
293 ENDPROC(save_boot_params)