3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
24 #ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
26 * Various SoCs need something special and SoC-specific up front in
27 * order to boot, allow them to set that in their boot0.h file and then
30 #include <asm/arch/boot0.h>
38 .quad CONFIG_SYS_TEXT_BASE
41 * These are defined in the linker script.
49 .quad __bss_start - _start
53 .quad __bss_end - _start
56 /* Allow the board to save important registers */
58 .globl save_boot_params_ret
61 #ifdef CONFIG_SYS_RESET_SCTRL
65 * Could be EL3/EL2/EL1, Initial State:
66 * Little Endian, MMU Disabled, i/dCache Disabled
69 switch_el x1, 3f, 2f, 1f
72 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
74 msr cptr_el3, xzr /* Enable FP/SIMD */
75 #ifdef COUNTER_FREQUENCY
76 ldr x0, =COUNTER_FREQUENCY
77 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
82 msr cptr_el2, x0 /* Enable FP/SIMD */
86 msr cpacr_el1, x0 /* Enable FP/SIMD */
90 * Enalbe SMPEN bit for coherency.
91 * This register is not architectural but at the moment
92 * this bit should be set for A53/A57/A72.
94 #ifdef CONFIG_ARMV8_SET_SMPEN
95 mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
100 /* Apply ARM core specific erratas */
104 * Cache/BPB/TLB Invalidate
105 * i-cache is invalidated before enabled in icache_enable()
106 * tlb is invalidated before mmu is enabled in dcache_enable()
107 * d-cache is invalidated before enabled in dcache_enable()
110 /* Processor specific initialization */
113 #if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
114 branch_if_master x0, x1, master_cpu
115 b spin_table_secondary_jump
117 #elif defined(CONFIG_ARMV8_MULTIENTRY)
118 branch_if_master x0, x1, master_cpu
125 ldr x1, =CPU_RELEASE_ADDR
128 br x0 /* branch to the given address */
129 #endif /* CONFIG_ARMV8_MULTIENTRY */
133 #ifdef CONFIG_SYS_RESET_SCTRL
135 switch_el x1, 3f, 2f, 1f
149 switch_el x1, 6f, 5f, 4f
162 b __asm_invalidate_tlb_all
166 /*-----------------------------------------------------------------------*/
168 WEAK(apply_core_errata)
170 mov x29, lr /* Save LR */
171 /* For now, we support Cortex-A57 specific errata only */
173 /* Check if we are running on a Cortex-A57 core */
174 branch_if_a57_core x0, apply_a57_core_errata
176 mov lr, x29 /* Restore LR */
179 apply_a57_core_errata:
181 #ifdef CONFIG_ARM_ERRATA_828024
182 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
183 /* Disable non-allocate hint of w-b-n-a memory type */
185 /* Disable write streaming no L1-allocate threshold */
187 /* Disable write streaming no-allocate threshold */
189 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
192 #ifdef CONFIG_ARM_ERRATA_826974
193 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
194 /* Disable speculative load execution ahead of a DMB */
196 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
199 #ifdef CONFIG_ARM_ERRATA_833471
200 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
201 /* FPSCR write flush.
202 * Note that in some cases where a flush is unnecessary this
203 could impact performance. */
205 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
208 #ifdef CONFIG_ARM_ERRATA_829520
209 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
210 /* Disable Indirect Predictor bit will prevent this erratum
212 * Note that in some cases where a flush is unnecessary this
213 could impact performance. */
215 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
218 #ifdef CONFIG_ARM_ERRATA_833069
219 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
220 /* Disable Enable Invalidates of BTB bit */
222 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
225 ENDPROC(apply_core_errata)
227 /*-----------------------------------------------------------------------*/
230 mov x29, lr /* Save LR */
232 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
233 branch_if_slave x0, 1f
237 #if defined(CONFIG_GICV3)
239 bl gic_init_secure_percpu
240 #elif defined(CONFIG_GICV2)
243 bl gic_init_secure_percpu
247 #ifdef CONFIG_ARMV8_MULTIENTRY
248 branch_if_master x0, x1, 2f
251 * Slave should wait for master clearing spin table.
252 * This sync prevent salves observing incorrect
253 * value of spin table and jumping to wrong place.
255 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
259 bl gic_wait_for_interrupt
263 * All slaves will enter EL2 and optionally EL1.
265 adr x4, lowlevel_in_el2
266 ldr x5, =ES_TO_AARCH64
267 bl armv8_switch_to_el2
270 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
271 adr x4, lowlevel_in_el1
272 ldr x5, =ES_TO_AARCH64
273 bl armv8_switch_to_el1
278 #endif /* CONFIG_ARMV8_MULTIENTRY */
281 mov lr, x29 /* Restore LR */
283 ENDPROC(lowlevel_init)
285 WEAK(smp_kick_all_cpus)
286 /* Kick secondary cpus up by SGI 0 interrupt */
287 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
289 b gic_kick_secondary_cpus
292 ENDPROC(smp_kick_all_cpus)
294 /*-----------------------------------------------------------------------*/
296 ENTRY(c_runtime_cpu_setup)
299 switch_el x1, 3f, 2f, 1f
308 ENDPROC(c_runtime_cpu_setup)
310 WEAK(save_boot_params)
311 b save_boot_params_ret /* back to my caller */
312 ENDPROC(save_boot_params)