1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * David Feng <fenghua@phytium.com.cn>
7 #include <asm-offsets.h>
9 #include <linux/linkage.h>
10 #include <asm/macro.h>
11 #include <asm/armv8/mmu.h>
13 /*************************************************************************
15 * Startup Code (reset vector)
17 *************************************************************************/
21 #if defined(LINUX_KERNEL_IMAGE_HEADER)
22 #include <asm/boot0-linux-kernel-header.h>
23 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
25 * Various SoCs need something special and SoC-specific up front in
26 * order to boot, allow them to set that in their boot0.h file and then
29 #include <asm/arch/boot0.h>
38 .quad CONFIG_SYS_TEXT_BASE
41 * These are defined in the linker script.
49 .quad __bss_start - _start
53 .quad __bss_end - _start
56 /* Allow the board to save important registers */
58 .globl save_boot_params_ret
61 #if CONFIG_POSITION_INDEPENDENT
63 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
64 * executed at a different address than it was linked at.
67 adr x0, _start /* x0 <- Runtime value of _start */
68 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
69 sub x9, x0, x1 /* x9 <- Run-vs-link offset */
70 adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
71 adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
73 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
74 ldr x4, [x2], #8 /* x4 <- addend */
75 cmp w1, #1027 /* relative fixup? */
77 /* relative fix: store addend plus offset at dest location */
87 #ifdef CONFIG_SYS_RESET_SCTRL
91 * Could be EL3/EL2/EL1, Initial State:
92 * Little Endian, MMU Disabled, i/dCache Disabled
95 switch_el x1, 3f, 2f, 1f
98 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
100 msr cptr_el3, xzr /* Enable FP/SIMD */
101 #ifdef COUNTER_FREQUENCY
102 ldr x0, =COUNTER_FREQUENCY
103 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
108 msr cptr_el2, x0 /* Enable FP/SIMD */
112 msr cpacr_el1, x0 /* Enable FP/SIMD */
116 * Enable SMPEN bit for coherency.
117 * This register is not architectural but at the moment
118 * this bit should be set for A53/A57/A72.
120 #ifdef CONFIG_ARMV8_SET_SMPEN
121 switch_el x1, 3f, 1f, 1f
123 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
125 msr S3_1_c15_c2_1, x0
129 /* Apply ARM core specific erratas */
133 * Cache/BPB/TLB Invalidate
134 * i-cache is invalidated before enabled in icache_enable()
135 * tlb is invalidated before mmu is enabled in dcache_enable()
136 * d-cache is invalidated before enabled in dcache_enable()
139 /* Processor specific initialization */
142 #if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
143 branch_if_master x0, x1, master_cpu
144 b spin_table_secondary_jump
146 #elif defined(CONFIG_ARMV8_MULTIENTRY)
147 branch_if_master x0, x1, master_cpu
154 ldr x1, =CPU_RELEASE_ADDR
157 br x0 /* branch to the given address */
158 #endif /* CONFIG_ARMV8_MULTIENTRY */
162 #ifdef CONFIG_SYS_RESET_SCTRL
164 switch_el x1, 3f, 2f, 1f
178 switch_el x1, 6f, 5f, 4f
191 b __asm_invalidate_tlb_all
195 /*-----------------------------------------------------------------------*/
197 WEAK(apply_core_errata)
199 mov x29, lr /* Save LR */
200 /* For now, we support Cortex-A53, Cortex-A57 specific errata */
202 /* Check if we are running on a Cortex-A53 core */
203 branch_if_a53_core x0, apply_a53_core_errata
205 /* Check if we are running on a Cortex-A57 core */
206 branch_if_a57_core x0, apply_a57_core_errata
208 mov lr, x29 /* Restore LR */
211 apply_a53_core_errata:
213 #ifdef CONFIG_ARM_ERRATA_855873
223 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
224 /* Enable data cache clean as data cache clean/invalidate */
226 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
230 apply_a57_core_errata:
232 #ifdef CONFIG_ARM_ERRATA_828024
233 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
234 /* Disable non-allocate hint of w-b-n-a memory type */
236 /* Disable write streaming no L1-allocate threshold */
238 /* Disable write streaming no-allocate threshold */
240 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
243 #ifdef CONFIG_ARM_ERRATA_826974
244 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
245 /* Disable speculative load execution ahead of a DMB */
247 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
250 #ifdef CONFIG_ARM_ERRATA_833471
251 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
252 /* FPSCR write flush.
253 * Note that in some cases where a flush is unnecessary this
254 could impact performance. */
256 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
259 #ifdef CONFIG_ARM_ERRATA_829520
260 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
261 /* Disable Indirect Predictor bit will prevent this erratum
263 * Note that in some cases where a flush is unnecessary this
264 could impact performance. */
266 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
269 #ifdef CONFIG_ARM_ERRATA_833069
270 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
271 /* Disable Enable Invalidates of BTB bit */
273 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
276 ENDPROC(apply_core_errata)
278 /*-----------------------------------------------------------------------*/
281 mov x29, lr /* Save LR */
283 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
284 branch_if_slave x0, 1f
288 #if defined(CONFIG_GICV3)
290 bl gic_init_secure_percpu
291 #elif defined(CONFIG_GICV2)
294 bl gic_init_secure_percpu
298 #ifdef CONFIG_ARMV8_MULTIENTRY
299 branch_if_master x0, x1, 2f
302 * Slave should wait for master clearing spin table.
303 * This sync prevent salves observing incorrect
304 * value of spin table and jumping to wrong place.
306 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
310 bl gic_wait_for_interrupt
314 * All slaves will enter EL2 and optionally EL1.
316 adr x4, lowlevel_in_el2
317 ldr x5, =ES_TO_AARCH64
318 bl armv8_switch_to_el2
321 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
322 adr x4, lowlevel_in_el1
323 ldr x5, =ES_TO_AARCH64
324 bl armv8_switch_to_el1
329 #endif /* CONFIG_ARMV8_MULTIENTRY */
332 mov lr, x29 /* Restore LR */
334 ENDPROC(lowlevel_init)
336 WEAK(smp_kick_all_cpus)
337 /* Kick secondary cpus up by SGI 0 interrupt */
338 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
340 b gic_kick_secondary_cpus
343 ENDPROC(smp_kick_all_cpus)
345 /*-----------------------------------------------------------------------*/
347 ENTRY(c_runtime_cpu_setup)
350 switch_el x1, 3f, 2f, 1f
359 ENDPROC(c_runtime_cpu_setup)
361 WEAK(save_boot_params)
362 b save_boot_params_ret /* back to my caller */
363 ENDPROC(save_boot_params)