3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
28 .quad CONFIG_SYS_TEXT_BASE
31 * These are defined in the linker script.
39 .quad __bss_start - _start
43 .quad __bss_end - _start
47 * Could be EL3/EL2/EL1, Initial State:
48 * Little Endian, MMU Disabled, i/dCache Disabled
51 switch_el x1, 3f, 2f, 1f
54 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
56 msr cptr_el3, xzr /* Enable FP/SIMD */
57 #ifdef COUNTER_FREQUENCY
58 ldr x0, =COUNTER_FREQUENCY
59 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
64 msr cptr_el2, x0 /* Enable FP/SIMD */
68 msr cpacr_el1, x0 /* Enable FP/SIMD */
71 /* Apply ARM core specific erratas */
75 * Cache/BPB/TLB Invalidate
76 * i-cache is invalidated before enabled in icache_enable()
77 * tlb is invalidated before mmu is enabled in dcache_enable()
78 * d-cache is invalidated before enabled in dcache_enable()
81 /* Processor specific initialization */
84 #ifdef CONFIG_ARMV8_MULTIENTRY
85 branch_if_master x0, x1, master_cpu
92 ldr x1, =CPU_RELEASE_ADDR
95 br x0 /* branch to the given address */
97 /* On the master CPU */
98 #endif /* CONFIG_ARMV8_MULTIENTRY */
102 /*-----------------------------------------------------------------------*/
104 WEAK(apply_core_errata)
106 mov x29, lr /* Save LR */
107 /* For now, we support Cortex-A57 specific errata only */
109 /* Check if we are running on a Cortex-A57 core */
110 branch_if_a57_core x0, apply_a57_core_errata
112 mov lr, x29 /* Restore LR */
115 apply_a57_core_errata:
117 #ifdef CONFIG_ARM_ERRATA_828024
118 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
119 /* Disable non-allocate hint of w-b-n-a memory type */
121 /* Disable write streaming no L1-allocate threshold */
123 /* Disable write streaming no-allocate threshold */
125 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
128 #ifdef CONFIG_ARM_ERRATA_826974
129 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
130 /* Disable speculative load execution ahead of a DMB */
132 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
135 #ifdef CONFIG_ARM_ERRATA_833069
136 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
137 /* Disable Enable Invalidates of BTB bit */
139 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
142 ENDPROC(apply_core_errata)
144 /*-----------------------------------------------------------------------*/
147 mov x29, lr /* Save LR */
149 #ifndef CONFIG_ARMV8_MULTIENTRY
151 * For single-entry systems the lowlevel init is very simple.
156 #else /* CONFIG_ARMV8_MULTIENTRY is set */
158 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
159 branch_if_slave x0, 1f
163 #if defined(CONFIG_GICV3)
165 bl gic_init_secure_percpu
166 #elif defined(CONFIG_GICV2)
169 bl gic_init_secure_percpu
173 branch_if_master x0, x1, 2f
176 * Slave should wait for master clearing spin table.
177 * This sync prevent salves observing incorrect
178 * value of spin table and jumping to wrong place.
180 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
184 bl gic_wait_for_interrupt
188 * All slaves will enter EL2 and optionally EL1.
190 bl armv8_switch_to_el2
191 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
192 bl armv8_switch_to_el1
195 #endif /* CONFIG_ARMV8_MULTIENTRY */
198 mov lr, x29 /* Restore LR */
200 ENDPROC(lowlevel_init)
202 WEAK(smp_kick_all_cpus)
203 /* Kick secondary cpus up by SGI 0 interrupt */
204 mov x29, lr /* Save LR */
205 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
207 bl gic_kick_secondary_cpus
209 mov lr, x29 /* Restore LR */
211 ENDPROC(smp_kick_all_cpus)
213 /*-----------------------------------------------------------------------*/
215 ENTRY(c_runtime_cpu_setup)
218 switch_el x1, 3f, 2f, 1f
227 ENDPROC(c_runtime_cpu_setup)