3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
10 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/armv8/mmu.h>
14 /*************************************************************************
16 * Startup Code (reset vector)
18 *************************************************************************/
28 .quad CONFIG_SYS_TEXT_BASE
31 * These are defined in the linker script.
39 .quad __bss_start - _start
43 .quad __bss_end - _start
47 * Could be EL3/EL2/EL1, Initial State:
48 * Little Endian, MMU Disabled, i/dCache Disabled
51 switch_el x1, 3f, 2f, 1f
54 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
56 msr cptr_el3, xzr /* Enable FP/SIMD */
57 ldr x0, =COUNTER_FREQUENCY
58 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
62 msr cptr_el2, x0 /* Enable FP/SIMD */
66 msr cpacr_el1, x0 /* Enable FP/SIMD */
69 /* Apply ARM core specific erratas */
73 * Cache/BPB/TLB Invalidate
74 * i-cache is invalidated before enabled in icache_enable()
75 * tlb is invalidated before mmu is enabled in dcache_enable()
76 * d-cache is invalidated before enabled in dcache_enable()
79 /* Processor specific initialization */
82 #ifdef CONFIG_ARMV8_MULTIENTRY
83 branch_if_master x0, x1, master_cpu
90 ldr x1, =CPU_RELEASE_ADDR
93 br x0 /* branch to the given address */
95 /* On the master CPU */
96 #endif /* CONFIG_ARMV8_MULTIENTRY */
100 /*-----------------------------------------------------------------------*/
102 WEAK(apply_core_errata)
104 mov x29, lr /* Save LR */
105 /* For now, we support Cortex-A57 specific errata only */
107 /* Check if we are running on a Cortex-A57 core */
108 branch_if_a57_core x0, apply_a57_core_errata
110 mov lr, x29 /* Restore LR */
113 apply_a57_core_errata:
115 #ifdef CONFIG_ARM_ERRATA_828024
116 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
117 /* Disable non-allocate hint of w-b-n-a memory type */
119 /* Disable write streaming no L1-allocate threshold */
121 /* Disable write streaming no-allocate threshold */
123 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
126 #ifdef CONFIG_ARM_ERRATA_826974
127 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
128 /* Disable speculative load execution ahead of a DMB */
130 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
133 #ifdef CONFIG_ARM_ERRATA_833069
134 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
135 /* Disable Enable Invalidates of BTB bit */
137 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
140 ENDPROC(apply_core_errata)
142 /*-----------------------------------------------------------------------*/
145 mov x29, lr /* Save LR */
147 #ifndef CONFIG_ARMV8_MULTIENTRY
149 * For single-entry systems the lowlevel init is very simple.
154 #else /* CONFIG_ARMV8_MULTIENTRY is set */
156 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
157 branch_if_slave x0, 1f
161 #if defined(CONFIG_GICV3)
163 bl gic_init_secure_percpu
164 #elif defined(CONFIG_GICV2)
167 bl gic_init_secure_percpu
171 branch_if_master x0, x1, 2f
174 * Slave should wait for master clearing spin table.
175 * This sync prevent salves observing incorrect
176 * value of spin table and jumping to wrong place.
178 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
182 bl gic_wait_for_interrupt
186 * All slaves will enter EL2 and optionally EL1.
188 bl armv8_switch_to_el2
189 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
190 bl armv8_switch_to_el1
193 #endif /* CONFIG_ARMV8_MULTIENTRY */
196 mov lr, x29 /* Restore LR */
198 ENDPROC(lowlevel_init)
200 WEAK(smp_kick_all_cpus)
201 /* Kick secondary cpus up by SGI 0 interrupt */
202 mov x29, lr /* Save LR */
203 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
205 bl gic_kick_secondary_cpus
207 mov lr, x29 /* Restore LR */
209 ENDPROC(smp_kick_all_cpus)
211 /*-----------------------------------------------------------------------*/
213 ENTRY(c_runtime_cpu_setup)
216 switch_el x1, 3f, 2f, 1f
225 ENDPROC(c_runtime_cpu_setup)