2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clk.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 unsigned long get_uart_clk(int dev_id)
17 u32 ver = zynqmp_get_silicon_version();
20 case ZYNQMP_CSU_VERSION_VELOCE:
22 case ZYNQMP_CSU_VERSION_EP108:
24 case ZYNQMP_CSU_VERSION_QEMU:
31 unsigned long zynqmp_get_system_timer_freq(void)
33 u32 ver = zynqmp_get_silicon_version();
36 case ZYNQMP_CSU_VERSION_VELOCE:
38 case ZYNQMP_CSU_VERSION_EP108:
40 case ZYNQMP_CSU_VERSION_QEMU:
49 * set_cpu_clk_info() - Initialize clock framework
50 * Always returns zero.
52 * This function is called from common code after relocation and sets up the
53 * clock framework. The framework must not be used before this function had been
56 int set_cpu_clk_info(void)
58 gd->cpu_clk = get_tbclk();
60 /* Support Veloce to show at least 1MHz via bdi */
61 if (gd->cpu_clk > 1000000)
62 gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
64 gd->bd->bi_arm_freq = 1;
66 gd->bd->bi_dsp_freq = 0;