git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv8/zynqmp/cpu.c

   1 /*
   2  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/hardware.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/armv8/mmu.h>
  12 #include <asm/io.h>
  13
  14 #define ZYNQ_SILICON_VER_MASK   0xF000
  15 #define ZYNQ_SILICON_VER_SHIFT  12
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static struct mm_region zynqmp_mem_map[] = {
  20 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  21         {
  22                 .virt = 0x0UL,
  23                 .phys = 0x0UL,
  24                 .size = 0x80000000UL,
  25                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  26                          PTE_BLOCK_INNER_SHARE
  27         },
  28 #endif
  29         {
  30                 .virt = 0x80000000UL,
  31                 .phys = 0x80000000UL,
  32                 .size = 0x70000000UL,
  33                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  34                          PTE_BLOCK_NON_SHARE |
  35                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  36         },
  37         {
  38                 .virt = 0xf8000000UL,
  39                 .phys = 0xf8000000UL,
  40                 .size = 0x07e00000UL,
  41                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  42                          PTE_BLOCK_NON_SHARE |
  43                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  44         }, {
  45 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  46                 .virt = 0xffe00000UL,
  47                 .phys = 0xffe00000UL,
  48                 .size = 0x00200000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  50                          PTE_BLOCK_INNER_SHARE
  51         }, {
  52 #endif
  53                 .virt = 0x400000000UL,
  54                 .phys = 0x400000000UL,
  55                 .size = 0x400000000UL,
  56                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  57                          PTE_BLOCK_NON_SHARE |
  58                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  59         },
  60 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  61         {
  62                 .virt = 0x800000000UL,
  63                 .phys = 0x800000000UL,
  64                 .size = 0x800000000UL,
  65                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  66                          PTE_BLOCK_INNER_SHARE
  67         },
  68 #endif
  69         {
  70                 .virt = 0x1000000000UL,
  71                 .phys = 0x1000000000UL,
  72                 .size = 0xf000000000UL,
  73                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  74                          PTE_BLOCK_NON_SHARE |
  75                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  76         }, {
  77                 /* List terminator */
  78                 0,
  79         }
  80 };
  81 struct mm_region *mem_map = zynqmp_mem_map;
  82
  83 u64 get_page_table_size(void)
  84 {
  85         return 0x14000;
  86 }
  87
  88 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
  89 int reserve_mmu(void)
  90 {
  91         initialize_tcm(TCM_LOCK);
  92         memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
  93         gd->arch.tlb_size = PGTABLE_SIZE;
  94         gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
  95
  96         return 0;
  97 }
  98 #endif
  99
 100 static unsigned int zynqmp_get_silicon_version_secure(void)
 101 {
 102         u32 ver;
 103
 104         ver = readl(&csu_base->version);
 105         ver &= ZYNQMP_SILICON_VER_MASK;
 106         ver >>= ZYNQMP_SILICON_VER_SHIFT;
 107
 108         return ver;
 109 }
 110
 111 unsigned int zynqmp_get_silicon_version(void)
 112 {
 113         if (current_el() == 3)
 114                 return zynqmp_get_silicon_version_secure();
 115
 116         gd->cpu_clk = get_tbclk();
 117
 118         switch (gd->cpu_clk) {
 119         case 0 ... 1000000:
 120                 return ZYNQMP_CSU_VERSION_VELOCE;
 121         case 50000000:
 122                 return ZYNQMP_CSU_VERSION_QEMU;
 123         case 4000000:
 124                 return ZYNQMP_CSU_VERSION_EP108;
 125         }
 126
 127         return ZYNQMP_CSU_VERSION_SILICON;
 128 }
 129
 130 #define ZYNQMP_MMIO_READ        0xC2000014
 131 #define ZYNQMP_MMIO_WRITE       0xC2000013
 132
 133 int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
 134                               u32 arg3, u32 *ret_payload)
 135 {
 136         /*
 137          * Added SIP service call Function Identifier
 138          * Make sure to stay in x0 register
 139          */
 140         struct pt_regs regs;
 141
 142         regs.regs[0] = pm_api_id;
 143         regs.regs[1] = ((u64)arg1 << 32) | arg0;
 144         regs.regs[2] = ((u64)arg3 << 32) | arg2;
 145
 146         smc_call(&regs);
 147
 148         if (ret_payload != NULL) {
 149                 ret_payload[0] = (u32)regs.regs[0];
 150                 ret_payload[1] = upper_32_bits(regs.regs[0]);
 151                 ret_payload[2] = (u32)regs.regs[1];
 152                 ret_payload[3] = upper_32_bits(regs.regs[1]);
 153                 ret_payload[4] = (u32)regs.regs[2];
 154         }
 155
 156         return regs.regs[0];
 157 }
 158
 159 #define ZYNQMP_SIP_SVC_GET_API_VERSION          0xC2000001
 160
 161 #define ZYNQMP_PM_VERSION_MAJOR         0
 162 #define ZYNQMP_PM_VERSION_MINOR         3
 163 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT   16
 164 #define ZYNQMP_PM_VERSION_MINOR_MASK    0xFFFF
 165
 166 #define ZYNQMP_PM_VERSION       \
 167         ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
 168                                  ZYNQMP_PM_VERSION_MINOR)
 169
 170 #if defined(CONFIG_CLK_ZYNQMP)
 171 void zynqmp_pmufw_version(void)
 172 {
 173         int ret;
 174         u32 ret_payload[PAYLOAD_ARG_CNT];
 175         u32 pm_api_version;
 176
 177         ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
 178                          ret_payload);
 179         pm_api_version = ret_payload[1];
 180
 181         if (ret)
 182                 panic("PMUFW is not found - Please load it!\n");
 183
 184         printf("PMUFW:\tv%d.%d\n",
 185                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 186                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 187
 188         if (pm_api_version != ZYNQMP_PM_VERSION)
 189                 panic("PMUFW version error. Expected: v%d.%d\n",
 190                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 191 }
 192 #endif
 193
 194 static int zynqmp_mmio_rawwrite(const u32 address,
 195                       const u32 mask,
 196                       const u32 value)
 197 {
 198         u32 data;
 199         u32 value_local = value;
 200
 201         zynqmp_mmio_read(address, &data);
 202         data &= ~mask;
 203         value_local &= mask;
 204         value_local |= data;
 205         writel(value_local, (ulong)address);
 206         return 0;
 207 }
 208
 209 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 210 {
 211         *value = readl((ulong)address);
 212         return 0;
 213 }
 214
 215 int zynqmp_mmio_write(const u32 address,
 216                       const u32 mask,
 217                       const u32 value)
 218 {
 219         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 220                 return zynqmp_mmio_rawwrite(address, mask, value);
 221         else
 222                 return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
 223                                   value, 0, NULL);
 224
 225         return -EINVAL;
 226 }
 227
 228 int zynqmp_mmio_read(const u32 address, u32 *value)
 229 {
 230         u32 ret_payload[PAYLOAD_ARG_CNT];
 231         u32 ret;
 232
 233         if (!value)
 234                 return -EINVAL;
 235
 236         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 237                 ret = zynqmp_mmio_rawread(address, value);
 238         } else {
 239                 ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
 240                                  0, ret_payload);
 241                 *value = ret_payload[1];
 242         }
 243
 244         return ret;
 245 }