git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv8/zynqmp/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/hardware.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <asm/armv8/mmu.h>
  11 #include <asm/io.h>
  12
  13 #define ZYNQ_SILICON_VER_MASK   0xF000
  14 #define ZYNQ_SILICON_VER_SHIFT  12
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static struct mm_region zynqmp_mem_map[] = {
  19 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  20         {
  21                 .virt = 0x0UL,
  22                 .phys = 0x0UL,
  23                 .size = 0x80000000UL,
  24                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  25                          PTE_BLOCK_INNER_SHARE
  26         },
  27 #endif
  28         {
  29                 .virt = 0x80000000UL,
  30                 .phys = 0x80000000UL,
  31                 .size = 0x70000000UL,
  32                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  33                          PTE_BLOCK_NON_SHARE |
  34                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  35         },
  36         {
  37                 .virt = 0xf8000000UL,
  38                 .phys = 0xf8000000UL,
  39                 .size = 0x07e00000UL,
  40                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  41                          PTE_BLOCK_NON_SHARE |
  42                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  43         }, {
  44 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  45                 .virt = 0xffe00000UL,
  46                 .phys = 0xffe00000UL,
  47                 .size = 0x00200000UL,
  48                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  49                          PTE_BLOCK_INNER_SHARE
  50         }, {
  51 #endif
  52                 .virt = 0x400000000UL,
  53                 .phys = 0x400000000UL,
  54                 .size = 0x400000000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56                          PTE_BLOCK_NON_SHARE |
  57                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58         },
  59 #if !defined(CONFIG_ZYNQMP_NO_DDR)
  60         {
  61                 .virt = 0x800000000UL,
  62                 .phys = 0x800000000UL,
  63                 .size = 0x800000000UL,
  64                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  65                          PTE_BLOCK_INNER_SHARE
  66         },
  67 #endif
  68         {
  69                 .virt = 0x1000000000UL,
  70                 .phys = 0x1000000000UL,
  71                 .size = 0xf000000000UL,
  72                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  73                          PTE_BLOCK_NON_SHARE |
  74                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  75         }, {
  76                 /* List terminator */
  77                 0,
  78         }
  79 };
  80 struct mm_region *mem_map = zynqmp_mem_map;
  81
  82 u64 get_page_table_size(void)
  83 {
  84         return 0x14000;
  85 }
  86
  87 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
  88 int reserve_mmu(void)
  89 {
  90         initialize_tcm(TCM_LOCK);
  91         memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
  92         gd->arch.tlb_size = PGTABLE_SIZE;
  93         gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
  94
  95         return 0;
  96 }
  97 #endif
  98
  99 static unsigned int zynqmp_get_silicon_version_secure(void)
 100 {
 101         u32 ver;
 102
 103         ver = readl(&csu_base->version);
 104         ver &= ZYNQMP_SILICON_VER_MASK;
 105         ver >>= ZYNQMP_SILICON_VER_SHIFT;
 106
 107         return ver;
 108 }
 109
 110 unsigned int zynqmp_get_silicon_version(void)
 111 {
 112         if (current_el() == 3)
 113                 return zynqmp_get_silicon_version_secure();
 114
 115         gd->cpu_clk = get_tbclk();
 116
 117         switch (gd->cpu_clk) {
 118         case 0 ... 1000000:
 119                 return ZYNQMP_CSU_VERSION_VELOCE;
 120         case 50000000:
 121                 return ZYNQMP_CSU_VERSION_QEMU;
 122         case 4000000:
 123                 return ZYNQMP_CSU_VERSION_EP108;
 124         }
 125
 126         return ZYNQMP_CSU_VERSION_SILICON;
 127 }
 128
 129 #define ZYNQMP_MMIO_READ        0xC2000014
 130 #define ZYNQMP_MMIO_WRITE       0xC2000013
 131
 132 int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
 133                               u32 arg3, u32 *ret_payload)
 134 {
 135         /*
 136          * Added SIP service call Function Identifier
 137          * Make sure to stay in x0 register
 138          */
 139         struct pt_regs regs;
 140
 141         regs.regs[0] = pm_api_id;
 142         regs.regs[1] = ((u64)arg1 << 32) | arg0;
 143         regs.regs[2] = ((u64)arg3 << 32) | arg2;
 144
 145         smc_call(&regs);
 146
 147         if (ret_payload != NULL) {
 148                 ret_payload[0] = (u32)regs.regs[0];
 149                 ret_payload[1] = upper_32_bits(regs.regs[0]);
 150                 ret_payload[2] = (u32)regs.regs[1];
 151                 ret_payload[3] = upper_32_bits(regs.regs[1]);
 152                 ret_payload[4] = (u32)regs.regs[2];
 153         }
 154
 155         return regs.regs[0];
 156 }
 157
 158 #define ZYNQMP_SIP_SVC_GET_API_VERSION          0xC2000001
 159
 160 #define ZYNQMP_PM_VERSION_MAJOR         0
 161 #define ZYNQMP_PM_VERSION_MINOR         3
 162 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT   16
 163 #define ZYNQMP_PM_VERSION_MINOR_MASK    0xFFFF
 164
 165 #define ZYNQMP_PM_VERSION       \
 166         ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
 167                                  ZYNQMP_PM_VERSION_MINOR)
 168
 169 #if defined(CONFIG_CLK_ZYNQMP)
 170 void zynqmp_pmufw_version(void)
 171 {
 172         int ret;
 173         u32 ret_payload[PAYLOAD_ARG_CNT];
 174         u32 pm_api_version;
 175
 176         ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
 177                          ret_payload);
 178         pm_api_version = ret_payload[1];
 179
 180         if (ret)
 181                 panic("PMUFW is not found - Please load it!\n");
 182
 183         printf("PMUFW:\tv%d.%d\n",
 184                pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
 185                pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
 186
 187         if (pm_api_version < ZYNQMP_PM_VERSION)
 188                 panic("PMUFW version error. Expected: v%d.%d\n",
 189                       ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
 190 }
 191 #endif
 192
 193 static int zynqmp_mmio_rawwrite(const u32 address,
 194                       const u32 mask,
 195                       const u32 value)
 196 {
 197         u32 data;
 198         u32 value_local = value;
 199
 200         zynqmp_mmio_read(address, &data);
 201         data &= ~mask;
 202         value_local &= mask;
 203         value_local |= data;
 204         writel(value_local, (ulong)address);
 205         return 0;
 206 }
 207
 208 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
 209 {
 210         *value = readl((ulong)address);
 211         return 0;
 212 }
 213
 214 int zynqmp_mmio_write(const u32 address,
 215                       const u32 mask,
 216                       const u32 value)
 217 {
 218         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
 219                 return zynqmp_mmio_rawwrite(address, mask, value);
 220         else
 221                 return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
 222                                   value, 0, NULL);
 223
 224         return -EINVAL;
 225 }
 226
 227 int zynqmp_mmio_read(const u32 address, u32 *value)
 228 {
 229         u32 ret_payload[PAYLOAD_ARG_CNT];
 230         u32 ret;
 231
 232         if (!value)
 233                 return -EINVAL;
 234
 235         if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
 236                 ret = zynqmp_mmio_rawread(address, value);
 237         } else {
 238                 ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
 239                                  0, ret_payload);
 240                 *value = ret_payload[1];
 241         }
 242
 243         return ret;
 244 }