1 /* vi: set ts=8 sw=8 noet: */
3 * u-boot - Startup Code for XScale IXP
5 * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
7 * Based on startup code example contained in the
8 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm-offsets.h>
33 #include <asm/arch/ixp425.h>
35 #define MMU_Control_M 0x001 /* Enable MMU */
36 #define MMU_Control_A 0x002 /* Enable address alignment faults */
37 #define MMU_Control_C 0x004 /* Enable cache */
38 #define MMU_Control_W 0x008 /* Enable write-buffer */
39 #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
40 #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
41 #define MMU_Control_L 0x040 /* Compatability: */
42 #define MMU_Control_B 0x080 /* Enable Big-Endian */
43 #define MMU_Control_S 0x100 /* Enable system protection */
44 #define MMU_Control_R 0x200 /* Enable ROM protection */
45 #define MMU_Control_I 0x1000 /* Enable Instruction cache */
46 #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
54 .macro DELAY_FOR cycles, reg0
60 /* wait for coprocessor write complete */
62 mrc p15,0,\reg,c2,c0,0
70 ldr pc, _undefined_instruction
71 ldr pc, _software_interrupt
72 ldr pc, _prefetch_abort
79 _undefined_instruction: .word undefined_instruction
80 _software_interrupt: .word software_interrupt
81 _prefetch_abort: .word prefetch_abort
82 _data_abort: .word data_abort
83 _not_used: .word not_used
87 .balignl 16,0xdeadbeef
91 * Startup Code (reset vector)
93 * do important init only if we don't start from memory!
94 * - relocate armboot to ram
96 * - jump to second stage
101 .word CONFIG_SYS_TEXT_BASE
104 * These are defined in the board-specific linker script.
105 * Subtracting _start from them lets the linker put their
106 * relative position in the executable instead of leaving
109 .globl _bss_start_ofs
111 .word __bss_start - _start
115 .word __bss_end__ - _start
121 #ifdef CONFIG_USE_IRQ
122 /* IRQ stack memory (calculated at run-time) */
123 .globl IRQ_STACK_START
127 /* IRQ stack memory (calculated at run-time) */
128 .globl FIQ_STACK_START
133 /* IRQ stack memory (calculated at run-time) + 8 bytes */
134 .globl IRQ_STACK_START_IN
139 * the actual reset code
143 /* disable mmu, set big-endian */
145 mcr p15, 0, r0, c1, c0, 0
148 /* invalidate I & D caches & BTB */
149 mcr p15, 0, r0, c7, c7, 0
152 /* invalidate I & Data TLB */
153 mcr p15, 0, r0, c8, c7, 0
156 /* drain write and fill buffers */
157 mcr p15, 0, r0, c7, c10, 4
160 /* disable write buffer coalescing */
161 mrc p15, 0, r0, c1, c0, 1
163 mcr p15, 0, r0, c1, c0, 1
166 /* set EXP CS0 to the optimum timing */
167 ldr r1, =CONFIG_SYS_EXP_CS0
168 ldr r2, =IXP425_EXP_CS0
171 /* make sure flash is visible at 0 */
172 mov r1, #CONFIG_SYS_SDR_CONFIG
173 ldr r2, =IXP425_SDR_CONFIG
176 /* disable refresh cycles */
178 ldr r3, =IXP425_SDR_REFRESH
181 /* send nop command */
183 ldr r4, =IXP425_SDR_IR
187 /* set SDRAM internal refresh val */
188 ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
192 /* send precharge-all command to close all open banks */
197 /* provide 8 auto-refresh cycles */
205 /* set mode register in sdram */
206 mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
210 /* send normal operation command */
215 /* invalidate I & D caches & BTB */
216 mcr p15, 0, r0, c7, c7, 0
219 /* invalidate I & Data TLB */
220 mcr p15, 0, r0, c8, c7, 0
223 /* drain write and fill buffers */
224 mcr p15, 0, r0, c7, c10, 4
227 /* remove flash mirror at 0x00000000 */
228 ldr r2, =IXP425_EXP_CFG0
230 bic r1, r1, #0x80000000
233 /* invalidate I & Data TLB */
234 mcr p15, 0, r0, c8, c7, 0
238 mrc p15, 0, r0, c1, c0, 0
239 orr r0, r0, #MMU_Control_I
240 mcr p15, 0, r0, c1, c0, 0
243 mrs r0,cpsr /* set the cpu to SVC32 mode */
244 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
248 /* Set initial stackpointer in SDRAM to call board_init_f */
250 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
251 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
255 /*------------------------------------------------------------------------------*/
258 * void relocate_code (addr_sp, gd, addr_moni)
260 * This "function" does not return, instead it continues in RAM
261 * after relocating the monitor code.
266 mov r4, r0 /* save addr_sp */
267 mov r5, r1 /* save addr of gd */
268 mov r6, r2 /* save addr of destination */
270 /* Set up the stack */
276 beq clear_bss /* skip relocation */
277 mov r1, r6 /* r1 <- scratch for copy_loop */
278 ldr r3, _bss_start_ofs
279 add r2, r0, r3 /* r2 <- source end address */
282 ldmia r0!, {r9-r10} /* copy from source address [r0] */
283 stmia r1!, {r9-r10} /* copy to target address [r1] */
284 cmp r0, r2 /* until source end address [r2] */
287 #ifndef CONFIG_SPL_BUILD
289 * fix .rel.dyn relocations
291 ldr r0, _TEXT_BASE /* r0 <- Text base */
292 sub r9, r6, r0 /* r9 <- relocation offset */
293 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
294 add r10, r10, r0 /* r10 <- sym table in FLASH */
295 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
296 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
297 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
298 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
300 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
301 add r0, r0, r9 /* r0 <- location to fix up in RAM */
304 cmp r7, #23 /* relative fixup? */
306 cmp r7, #2 /* absolute fixup? */
308 /* ignore unknown type of fixup */
311 /* absolute fix: set location to (offset) symbol value */
312 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
313 add r1, r10, r1 /* r1 <- address of symbol in table */
314 ldr r1, [r1, #4] /* r1 <- symbol value */
315 add r1, r1, r9 /* r1 <- relocated sym addr */
318 /* relative fix: increase location by offset */
323 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
329 #ifndef CONFIG_SPL_BUILD
330 ldr r0, _bss_start_ofs
332 mov r4, r6 /* reloc addr */
335 mov r2, #0x00000000 /* clear */
337 clbss_l:str r2, [r0] /* clear loop... */
347 * We are done. Do not return, instead branch to second part of board
348 * initialization, now running from RAM.
350 ldr r0, _board_init_r_ofs
354 /* setup parameters for board_init_r */
355 mov r0, r5 /* gd_t */
356 mov r1, r6 /* dest_addr */
361 .word board_init_r - _start
364 .word __rel_dyn_start - _start
366 .word __rel_dyn_end - _start
368 .word __dynsym_start - _start
370 /****************************************************************************/
372 /* Interrupt handling */
374 /****************************************************************************/
376 /* IRQ stack frame */
378 #define S_FRAME_SIZE 72
400 #define MODE_SVC 0x13
402 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
404 .macro bad_save_user_regs
405 sub sp, sp, #S_FRAME_SIZE
406 stmia sp, {r0 - r12} /* Calling r0-r12 */
409 ldr r2, IRQ_STACK_START_IN
410 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
411 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
415 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
420 /* use irq_save_user_regs / irq_restore_user_regs for */
421 /* IRQ/FIQ handling */
423 .macro irq_save_user_regs
424 sub sp, sp, #S_FRAME_SIZE
425 stmia sp, {r0 - r12} /* Calling r0-r12 */
427 stmdb r8, {sp, lr}^ /* Calling SP, LR */
428 str lr, [r8, #0] /* Save calling PC */
430 str r6, [r8, #4] /* Save CPSR */
431 str r0, [r8, #8] /* Save OLD_R0 */
435 .macro irq_restore_user_regs
436 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
438 ldr lr, [sp, #S_PC] @ Get PC
439 add sp, sp, #S_FRAME_SIZE
440 subs pc, lr, #4 @ return & move spsr_svc into cpsr
444 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
446 str lr, [r13] @ save caller lr / spsr
450 mov r13, #MODE_SVC @ prepare SVC-Mode
456 .macro get_irq_stack @ setup IRQ stack
457 ldr sp, IRQ_STACK_START
460 .macro get_fiq_stack @ setup FIQ stack
461 ldr sp, FIQ_STACK_START
465 /****************************************************************************/
467 /* exception handlers */
469 /****************************************************************************/
472 undefined_instruction:
475 bl do_undefined_instruction
481 bl do_software_interrupt
501 #ifdef CONFIG_USE_IRQ
508 irq_restore_user_regs
513 irq_save_user_regs /* someone ought to write a more */
514 bl do_fiq /* effiction fiq_save_user_regs */
515 irq_restore_user_regs
533 /****************************************************************************/
535 /* Reset function: Use Watchdog to reset */
537 /****************************************************************************/