1 /* vi: set ts=8 sw=8 noet: */
3 * u-boot - Startup Code for XScale IXP
5 * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
7 * Based on startup code example contained in the
8 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm-offsets.h>
33 #include <asm/arch/ixp425.h>
35 #define MMU_Control_M 0x001 /* Enable MMU */
36 #define MMU_Control_A 0x002 /* Enable address alignment faults */
37 #define MMU_Control_C 0x004 /* Enable cache */
38 #define MMU_Control_W 0x008 /* Enable write-buffer */
39 #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
40 #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
41 #define MMU_Control_L 0x040 /* Compatability: */
42 #define MMU_Control_B 0x080 /* Enable Big-Endian */
43 #define MMU_Control_S 0x100 /* Enable system protection */
44 #define MMU_Control_R 0x200 /* Enable ROM protection */
45 #define MMU_Control_I 0x1000 /* Enable Instruction cache */
46 #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
54 .macro DELAY_FOR cycles, reg0
60 /* wait for coprocessor write complete */
62 mrc p15,0,\reg,c2,c0,0
69 ldr pc, _undefined_instruction
70 ldr pc, _software_interrupt
71 ldr pc, _prefetch_abort
77 _undefined_instruction: .word undefined_instruction
78 _software_interrupt: .word software_interrupt
79 _prefetch_abort: .word prefetch_abort
80 _data_abort: .word data_abort
81 _not_used: .word not_used
85 .balignl 16,0xdeadbeef
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * - relocate armboot to ram
94 * - jump to second stage
99 .word CONFIG_SYS_TEXT_BASE
102 * These are defined in the board-specific linker script.
103 * Subtracting _start from them lets the linker put their
104 * relative position in the executable instead of leaving
107 .globl _bss_start_ofs
109 .word __bss_start - _start
113 .word __bss_end__ - _start
115 #ifdef CONFIG_USE_IRQ
116 /* IRQ stack memory (calculated at run-time) */
117 .globl IRQ_STACK_START
121 /* IRQ stack memory (calculated at run-time) */
122 .globl FIQ_STACK_START
127 /* IRQ stack memory (calculated at run-time) + 8 bytes */
128 .globl IRQ_STACK_START_IN
133 * the actual reset code
137 /* disable mmu, set big-endian */
139 mcr p15, 0, r0, c1, c0, 0
142 /* invalidate I & D caches & BTB */
143 mcr p15, 0, r0, c7, c7, 0
146 /* invalidate I & Data TLB */
147 mcr p15, 0, r0, c8, c7, 0
150 /* drain write and fill buffers */
151 mcr p15, 0, r0, c7, c10, 4
154 /* disable write buffer coalescing */
155 mrc p15, 0, r0, c1, c0, 1
157 mcr p15, 0, r0, c1, c0, 1
160 /* set EXP CS0 to the optimum timing */
161 ldr r1, =CONFIG_SYS_EXP_CS0
162 ldr r2, =IXP425_EXP_CS0
165 /* make sure flash is visible at 0 */
167 ldr r2, =IXP425_EXP_CFG0
169 orr r1, r1, #0x80000000
172 mov r1, #CONFIG_SYS_SDR_CONFIG
173 ldr r2, =IXP425_SDR_CONFIG
176 /* disable refresh cycles */
178 ldr r3, =IXP425_SDR_REFRESH
181 /* send nop command */
183 ldr r4, =IXP425_SDR_IR
187 /* set SDRAM internal refresh val */
188 ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
192 /* send precharge-all command to close all open banks */
197 /* provide 8 auto-refresh cycles */
205 /* set mode register in sdram */
206 mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
210 /* send normal operation command */
218 add r2, r0, #CONFIG_SYS_MONITOR_LEN
228 /* invalidate I & D caches & BTB */
229 mcr p15, 0, r0, c7, c7, 0
232 /* invalidate I & Data TLB */
233 mcr p15, 0, r0, c8, c7, 0
236 /* drain write and fill buffers */
237 mcr p15, 0, r0, c7, c10, 4
240 /* move flash to 0x50000000 */
241 ldr r2, =IXP425_EXP_CFG0
243 bic r1, r1, #0x80000000
253 /* invalidate I & Data TLB */
254 mcr p15, 0, r0, c8, c7, 0
258 mrc p15, 0, r0, c1, c0, 0
259 orr r0, r0, #MMU_Control_I
260 mcr p15, 0, r0, c1, c0, 0
263 mrs r0,cpsr /* set the cpu to SVC32 mode */
264 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
268 /* Set stackpointer in internal RAM to call board_init_f */
270 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
271 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
275 /*------------------------------------------------------------------------------*/
278 * void relocate_code (addr_sp, gd, addr_moni)
280 * This "function" does not return, instead it continues in RAM
281 * after relocating the monitor code.
286 mov r4, r0 /* save addr_sp */
287 mov r5, r1 /* save addr of gd */
288 mov r6, r2 /* save addr of destination */
290 /* Set up the stack */
296 beq clear_bss /* skip relocation */
297 mov r1, r6 /* r1 <- scratch for copy_loop */
298 ldr r3, _bss_start_ofs
299 add r2, r0, r3 /* r2 <- source end address */
302 ldmia r0!, {r9-r10} /* copy from source address [r0] */
303 stmia r1!, {r9-r10} /* copy to target address [r1] */
304 cmp r0, r2 /* until source end address [r2] */
307 #ifndef CONFIG_PRELOADER
309 * fix .rel.dyn relocations
311 ldr r0, _TEXT_BASE /* r0 <- Text base */
312 sub r9, r6, r0 /* r9 <- relocation offset */
313 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
314 add r10, r10, r0 /* r10 <- sym table in FLASH */
315 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
316 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
317 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
318 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
320 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
321 add r0, r0, r9 /* r0 <- location to fix up in RAM */
324 cmp r7, #23 /* relative fixup? */
326 cmp r7, #2 /* absolute fixup? */
328 /* ignore unknown type of fixup */
331 /* absolute fix: set location to (offset) symbol value */
332 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
333 add r1, r10, r1 /* r1 <- address of symbol in table */
334 ldr r1, [r1, #4] /* r1 <- symbol value */
335 add r1, r1, r9 /* r1 <- relocated sym addr */
338 /* relative fix: increase location by offset */
343 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
349 #ifndef CONFIG_PRELOADER
350 ldr r0, _bss_start_ofs
352 mov r4, r6 /* reloc addr */
355 mov r2, #0x00000000 /* clear */
357 clbss_l:str r2, [r0] /* clear loop... */
367 * We are done. Do not return, instead branch to second part of board
368 * initialization, now running from RAM.
370 ldr r0, _board_init_r_ofs
374 /* setup parameters for board_init_r */
375 mov r0, r5 /* gd_t */
376 mov r1, r6 /* dest_addr */
381 .word board_init_r - _start
384 .word __rel_dyn_start - _start
386 .word __rel_dyn_end - _start
388 .word __dynsym_start - _start
390 /****************************************************************************/
392 /* Interrupt handling */
394 /****************************************************************************/
396 /* IRQ stack frame */
398 #define S_FRAME_SIZE 72
420 #define MODE_SVC 0x13
422 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
424 .macro bad_save_user_regs
425 sub sp, sp, #S_FRAME_SIZE
426 stmia sp, {r0 - r12} /* Calling r0-r12 */
429 ldr r2, IRQ_STACK_START_IN
430 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
431 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
435 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
440 /* use irq_save_user_regs / irq_restore_user_regs for */
441 /* IRQ/FIQ handling */
443 .macro irq_save_user_regs
444 sub sp, sp, #S_FRAME_SIZE
445 stmia sp, {r0 - r12} /* Calling r0-r12 */
447 stmdb r8, {sp, lr}^ /* Calling SP, LR */
448 str lr, [r8, #0] /* Save calling PC */
450 str r6, [r8, #4] /* Save CPSR */
451 str r0, [r8, #8] /* Save OLD_R0 */
455 .macro irq_restore_user_regs
456 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
458 ldr lr, [sp, #S_PC] @ Get PC
459 add sp, sp, #S_FRAME_SIZE
460 subs pc, lr, #4 @ return & move spsr_svc into cpsr
464 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
466 str lr, [r13] @ save caller lr / spsr
470 mov r13, #MODE_SVC @ prepare SVC-Mode
476 .macro get_irq_stack @ setup IRQ stack
477 ldr sp, IRQ_STACK_START
480 .macro get_fiq_stack @ setup FIQ stack
481 ldr sp, FIQ_STACK_START
485 /****************************************************************************/
487 /* exception handlers */
489 /****************************************************************************/
492 undefined_instruction:
495 bl do_undefined_instruction
501 bl do_software_interrupt
521 #ifdef CONFIG_USE_IRQ
528 irq_restore_user_regs
533 irq_save_user_regs /* someone ought to write a more */
534 bl do_fiq /* effiction fiq_save_user_regs */
535 irq_restore_user_regs
553 /****************************************************************************/
555 /* Reset function: Use Watchdog to reset */
557 /****************************************************************************/
579 #ifdef CONFIG_USE_IRQ
581 .LC0: .word loops_per_jiffy
592 ldr r2, [r2] @ max = 0x0fffffff
593 mov r0, r0, lsr #11 @ max = 0x00003fff
594 mov r2, r2, lsr #11 @ max = 0x0003ffff
595 mul r0, r2, r0 @ max = 2^32-1
603 #endif /* CONFIG_USE_IRQ */