2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
79 * These are defined in the board-specific linker script.
90 /* IRQ stack memory (calculated at run-time) */
91 .globl IRQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) */
96 .globl FIQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) + 8 bytes */
102 .globl IRQ_STACK_START_IN
106 .globl _datarel_start
108 .word __datarel_start
110 .globl _datarelrolocal_start
111 _datarelrolocal_start:
112 .word __datarelrolocal_start
114 .globl _datarellocal_start
116 .word __datarellocal_start
118 .globl _datarelro_start
120 .word __datarelro_start
131 * the actual reset code
136 * set the cpu to SVC32 mode
143 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
144 #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
145 #define pCLKSET 0x80000420 /* clock divisor register */
147 /* disable watchdog, set watchdog control register to
148 * all zeros (default reset)
155 * mask all IRQs by setting all bits in the INTENC register (default)
161 /* FCLK:HCLK:PCLK = 1:2:2 */
162 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
165 @ ldr r1, =0x0005ee39 @ 1: 2: 4
169 * we do sys-critical inits only at reboot,
170 * not when booting from ram!
172 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
176 /* Set stackpointer in internal RAM to call board_init_f */
178 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
182 /*------------------------------------------------------------------------------*/
185 * void relocate_code (addr_sp, gd, addr_moni)
187 * This "function" does not return, instead it continues in RAM
188 * after relocating the monitor code.
193 mov r4, r0 /* save addr_sp */
194 mov r5, r1 /* save addr of gd */
195 mov r6, r2 /* save addr of destination */
196 mov r7, r2 /* save addr of destination */
198 /* Set up the stack */
205 sub r2, r3, r2 /* r2 <- size of armboot */
206 add r2, r0, r2 /* r2 <- source end address */
210 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
212 ldmia r0!, {r9-r10} /* copy from source address [r0] */
213 stmia r6!, {r9-r10} /* copy to target address [r1] */
214 cmp r0, r2 /* until source end address [r2] */
217 #ifndef CONFIG_PRELOADER
218 /* fix got entries */
219 ldr r1, _TEXT_BASE /* Text base */
220 mov r0, r7 /* reloc addr */
221 ldr r2, _got_start /* addr in Flash */
222 ldr r3, _got_end /* addr in Flash */
237 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
240 #ifndef CONFIG_PRELOADER
243 ldr r3, _TEXT_BASE /* Text base */
244 mov r4, r7 /* reloc addr */
249 mov r2, #0x00000000 /* clear */
251 clbss_l:str r2, [r0] /* clear loop... */
258 * We are done. Do not return, instead branch to second part of board
259 * initialization, now running from RAM.
262 ldr r2, _board_init_r
264 add r2, r2, r7 /* position from board_init_r in RAM */
265 /* setup parameters for board_init_r */
266 mov r0, r5 /* gd_t */
267 mov r1, r7 /* dest_addr */
272 _board_init_r: .word board_init_r
275 *************************************************************************
277 * CPU_init_critical registers
279 * setup important registers
280 * setup memory timing
282 *************************************************************************
288 * flush v4 I/D caches
291 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
292 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
295 * disable MMU stuff and caches
297 mrc p15, 0, r0, c1, c0, 0
298 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
299 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
300 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
301 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
302 orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
303 mcr p15, 0, r0, c1, c0, 0
307 * before relocating, we have to setup RAM timing
308 * because memory timing is board-dependend, you will
309 * find a lowlevel_init.S in your board directory.
319 *************************************************************************
323 *************************************************************************
329 #define S_FRAME_SIZE 72
351 #define MODE_SVC 0x13
355 * use bad_save_user_regs for abort/prefetch/undef/swi ...
356 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
359 .macro bad_save_user_regs
360 sub sp, sp, #S_FRAME_SIZE
361 stmia sp, {r0 - r12} @ Calling r0-r12
362 ldr r2, IRQ_STACK_START_IN
363 ldmia r2, {r2 - r3} @ get pc, cpsr
364 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
368 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
372 .macro irq_save_user_regs
373 sub sp, sp, #S_FRAME_SIZE
374 stmia sp, {r0 - r12} @ Calling r0-r12
376 stmdb r8, {sp, lr}^ @ Calling SP, LR
377 str lr, [r8, #0] @ Save calling PC
379 str r6, [r8, #4] @ Save CPSR
380 str r0, [r8, #8] @ Save OLD_R0
384 .macro irq_restore_user_regs
385 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
387 ldr lr, [sp, #S_PC] @ Get PC
388 add sp, sp, #S_FRAME_SIZE
389 subs pc, lr, #4 @ return & move spsr_svc into cpsr
393 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
395 str lr, [r13] @ save caller lr / spsr
399 mov r13, #MODE_SVC @ prepare SVC-Mode
406 .macro get_irq_stack @ setup IRQ stack
407 ldr sp, IRQ_STACK_START
410 .macro get_fiq_stack @ setup FIQ stack
411 ldr sp, FIQ_STACK_START
418 undefined_instruction:
421 bl do_undefined_instruction
427 bl do_software_interrupt
447 #ifdef CONFIG_USE_IRQ
454 irq_restore_user_regs
459 /* someone ought to write a more effiction fiq_save_user_regs */
462 irq_restore_user_regs
483 bl disable_interrupts
485 /* Disable watchdog */
494 /* Enable the watchdog */