2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
79 * These are defined in the board-specific linker script.
80 * Subtracting _start from them lets the linker put their
81 * relative position in the executable instead of leaving
86 .word __bss_start - _start
90 .word __bss_end__ - _start
97 /* IRQ stack memory (calculated at run-time) */
98 .globl IRQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) */
103 .globl FIQ_STACK_START
108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
109 .globl IRQ_STACK_START_IN
114 * the actual reset code
119 * set the cpu to SVC32 mode
126 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
127 #define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
128 #define pCLKSET 0x80000420 /* clock divisor register */
130 /* disable watchdog, set watchdog control register to
131 * all zeros (default reset)
138 * mask all IRQs by setting all bits in the INTENC register (default)
144 /* FCLK:HCLK:PCLK = 1:2:2 */
145 /* default FCLK is 200 MHz, using 14.7456 MHz fin */
148 @ ldr r1, =0x0005ee39 @ 1: 2: 4
152 * we do sys-critical inits only at reboot,
153 * not when booting from ram!
155 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
159 /* Set stackpointer in internal RAM to call board_init_f */
161 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
162 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
166 /*------------------------------------------------------------------------------*/
169 * void relocate_code (addr_sp, gd, addr_moni)
171 * This "function" does not return, instead it continues in RAM
172 * after relocating the monitor code.
177 mov r4, r0 /* save addr_sp */
178 mov r5, r1 /* save addr of gd */
179 mov r6, r2 /* save addr of destination */
181 /* Set up the stack */
187 beq clear_bss /* skip relocation */
188 mov r1, r6 /* r1 <- scratch for copy_loop */
189 ldr r3, _bss_start_ofs
190 add r2, r0, r3 /* r2 <- source end address */
193 ldmia r0!, {r9-r10} /* copy from source address [r0] */
194 stmia r1!, {r9-r10} /* copy to target address [r1] */
195 cmp r0, r2 /* until source end address [r2] */
198 #ifndef CONFIG_SPL_BUILD
200 * fix .rel.dyn relocations
202 ldr r0, _TEXT_BASE /* r0 <- Text base */
203 sub r9, r6, r0 /* r9 <- relocation offset */
204 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
205 add r10, r10, r0 /* r10 <- sym table in FLASH */
206 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
207 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
208 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
209 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
211 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
212 add r0, r0, r9 /* r0 <- location to fix up in RAM */
215 cmp r7, #23 /* relative fixup? */
217 cmp r7, #2 /* absolute fixup? */
219 /* ignore unknown type of fixup */
222 /* absolute fix: set location to (offset) symbol value */
223 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
224 add r1, r10, r1 /* r1 <- address of symbol in table */
225 ldr r1, [r1, #4] /* r1 <- symbol value */
226 add r1, r1, r9 /* r1 <- relocated sym addr */
229 /* relative fix: increase location by offset */
234 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
240 #ifndef CONFIG_SPL_BUILD
241 ldr r0, _bss_start_ofs
243 mov r4, r6 /* reloc addr */
246 mov r2, #0x00000000 /* clear */
248 clbss_l:cmp r0, r1 /* clear loop... */
249 bhs clbss_e /* if reached end of bss, exit */
257 * We are done. Do not return, instead branch to second part of board
258 * initialization, now running from RAM.
260 ldr r0, _board_init_r_ofs
264 /* setup parameters for board_init_r */
265 mov r0, r5 /* gd_t */
266 mov r1, r6 /* dest_addr */
271 .word board_init_r - _start
274 .word __rel_dyn_start - _start
276 .word __rel_dyn_end - _start
278 .word __dynsym_start - _start
281 *************************************************************************
283 * CPU_init_critical registers
285 * setup important registers
286 * setup memory timing
288 *************************************************************************
294 * flush v4 I/D caches
297 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
298 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
301 * disable MMU stuff and caches
303 mrc p15, 0, r0, c1, c0, 0
304 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
305 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
306 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
307 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
308 orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
309 mcr p15, 0, r0, c1, c0, 0
313 * before relocating, we have to setup RAM timing
314 * because memory timing is board-dependend, you will
315 * find a lowlevel_init.S in your board directory.
325 *************************************************************************
329 *************************************************************************
335 #define S_FRAME_SIZE 72
357 #define MODE_SVC 0x13
361 * use bad_save_user_regs for abort/prefetch/undef/swi ...
362 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
365 .macro bad_save_user_regs
366 sub sp, sp, #S_FRAME_SIZE
367 stmia sp, {r0 - r12} @ Calling r0-r12
368 ldr r2, IRQ_STACK_START_IN
369 ldmia r2, {r2 - r3} @ get pc, cpsr
370 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
374 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
378 .macro irq_save_user_regs
379 sub sp, sp, #S_FRAME_SIZE
380 stmia sp, {r0 - r12} @ Calling r0-r12
382 stmdb r8, {sp, lr}^ @ Calling SP, LR
383 str lr, [r8, #0] @ Save calling PC
385 str r6, [r8, #4] @ Save CPSR
386 str r0, [r8, #8] @ Save OLD_R0
390 .macro irq_restore_user_regs
391 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
393 ldr lr, [sp, #S_PC] @ Get PC
394 add sp, sp, #S_FRAME_SIZE
395 subs pc, lr, #4 @ return & move spsr_svc into cpsr
399 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
401 str lr, [r13] @ save caller lr / spsr
405 mov r13, #MODE_SVC @ prepare SVC-Mode
412 .macro get_irq_stack @ setup IRQ stack
413 ldr sp, IRQ_STACK_START
416 .macro get_fiq_stack @ setup FIQ stack
417 ldr sp, FIQ_STACK_START
424 undefined_instruction:
427 bl do_undefined_instruction
433 bl do_software_interrupt
453 #ifdef CONFIG_USE_IRQ
460 irq_restore_user_regs
465 /* someone ought to write a more effiction fiq_save_user_regs */
468 irq_restore_user_regs
489 bl disable_interrupts
491 /* Disable watchdog */
500 /* Enable the watchdog */