4 * (C) Copyright 2001-2002
5 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /************************************************************************/
28 /************************************************************************/
34 #include <linux/types.h>
35 #include <stdio_dev.h>
37 #include <asm/arch/pxa-regs.h>
44 /*----------------------------------------------------------------------*/
46 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
51 /* LCD outputs connected to a video DAC */
52 # define LCD_BPP LCD_COLOR8
54 /* you have to set lccr0 and lccr3 (including pcd) */
55 # define REG_LCCR0 0x003008f8
56 # define REG_LCCR3 0x0300FF01
58 /* 640x480x16 @ 61 Hz */
59 vidinfo_t panel_info = {
64 .vl_clkp = CONFIG_SYS_HIGH,
65 .vl_oep = CONFIG_SYS_HIGH,
66 .vl_hsp = CONFIG_SYS_HIGH,
67 .vl_vsp = CONFIG_SYS_HIGH,
68 .vl_dp = CONFIG_SYS_HIGH,
81 #endif /* CONFIG_PXA_VIDEO */
83 /*----------------------------------------------------------------------*/
84 #ifdef CONFIG_SHARP_LM8V31
86 # define LCD_BPP LCD_COLOR8
87 # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
89 /* you have to set lccr0 and lccr3 (including pcd) */
90 # define REG_LCCR0 0x0030087C
91 # define REG_LCCR3 0x0340FF08
93 vidinfo_t panel_info = {
98 .vl_clkp = CONFIG_SYS_HIGH,
99 .vl_oep = CONFIG_SYS_HIGH,
100 .vl_hsp = CONFIG_SYS_HIGH,
101 .vl_vsp = CONFIG_SYS_HIGH,
102 .vl_dp = CONFIG_SYS_HIGH,
115 #endif /* CONFIG_SHARP_LM8V31 */
116 /*----------------------------------------------------------------------*/
117 #ifdef CONFIG_VOIPAC_LCD
119 # define LCD_BPP LCD_COLOR8
120 # define LCD_INVERT_COLORS
122 /* you have to set lccr0 and lccr3 (including pcd) */
123 # define REG_LCCR0 0x043008f8
124 # define REG_LCCR3 0x0340FF08
126 vidinfo_t panel_info = {
131 .vl_clkp = CONFIG_SYS_HIGH,
132 .vl_oep = CONFIG_SYS_HIGH,
133 .vl_hsp = CONFIG_SYS_HIGH,
134 .vl_vsp = CONFIG_SYS_HIGH,
135 .vl_dp = CONFIG_SYS_HIGH,
148 #endif /* CONFIG_VOIPAC_LCD */
150 /*----------------------------------------------------------------------*/
151 #ifdef CONFIG_HITACHI_SX14
152 /* Hitachi SX14Q004-ZZA color STN LCD */
153 #define LCD_BPP LCD_COLOR8
155 /* you have to set lccr0 and lccr3 (including pcd) */
156 #define REG_LCCR0 0x00301079
157 #define REG_LCCR3 0x0340FF20
159 vidinfo_t panel_info = {
164 .vl_clkp = CONFIG_SYS_HIGH,
165 .vl_oep = CONFIG_SYS_HIGH,
166 .vl_hsp = CONFIG_SYS_HIGH,
167 .vl_vsp = CONFIG_SYS_HIGH,
168 .vl_dp = CONFIG_SYS_HIGH,
181 #endif /* CONFIG_HITACHI_SX14 */
183 /*----------------------------------------------------------------------*/
184 #ifdef CONFIG_LMS283GF05
186 # define LCD_BPP LCD_COLOR8
187 /*# define LCD_INVERT_COLORS*/
189 /* you have to set lccr0 and lccr3 (including pcd) */
190 # define REG_LCCR0 0x043008f8
191 # define REG_LCCR3 0x03b00009
193 vidinfo_t panel_info = {
198 .vl_clkp = CONFIG_SYS_HIGH,
199 .vl_oep = CONFIG_SYS_LOW,
200 .vl_hsp = CONFIG_SYS_LOW,
201 .vl_vsp = CONFIG_SYS_LOW,
202 .vl_dp = CONFIG_SYS_HIGH,
215 #endif /* CONFIG_LMS283GF05 */
217 /*----------------------------------------------------------------------*/
219 #if LCD_BPP == LCD_COLOR8
220 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
222 #if LCD_BPP == LCD_MONOCHROME
223 void lcd_initcolregs (void);
226 #ifdef NOT_USED_SO_FAR
227 void lcd_disable (void);
228 void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
229 #endif /* NOT_USED_SO_FAR */
231 void lcd_ctrl_init (void *lcdbase);
232 void lcd_enable (void);
238 void *lcd_base; /* Start of framebuffer memory */
239 void *lcd_console_address; /* Start of console buffer */
244 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
245 static void pxafb_setup_gpio (vidinfo_t *vid);
246 static void pxafb_enable_controller (vidinfo_t *vid);
247 static int pxafb_init (vidinfo_t *vid);
248 /************************************************************************/
250 /************************************************************************/
251 /* --------------- PXA chipset specific functions ------------------- */
252 /************************************************************************/
254 void lcd_ctrl_init (void *lcdbase)
256 pxafb_init_mem(lcdbase, &panel_info);
257 pxafb_init(&panel_info);
258 pxafb_setup_gpio(&panel_info);
259 pxafb_enable_controller(&panel_info);
262 /*----------------------------------------------------------------------*/
263 #ifdef NOT_USED_SO_FAR
265 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
268 #endif /* NOT_USED_SO_FAR */
270 /*----------------------------------------------------------------------*/
271 #if LCD_BPP == LCD_COLOR8
273 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
275 struct pxafb_info *fbi = &panel_info.pxa;
276 unsigned short *palette = (unsigned short *)fbi->palette;
279 if (regno < fbi->palette_size) {
280 val = ((red << 8) & 0xf800);
281 val |= ((green << 4) & 0x07e0);
282 val |= (blue & 0x001f);
284 #ifdef LCD_INVERT_COLORS
285 palette[regno] = ~val;
287 palette[regno] = val;
291 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
292 regno, &palette[regno],
296 #endif /* LCD_COLOR8 */
298 /*----------------------------------------------------------------------*/
299 #if LCD_BPP == LCD_MONOCHROME
300 void lcd_initcolregs (void)
302 struct pxafb_info *fbi = &panel_info.pxa;
303 cmap = (ushort *)fbi->palette;
306 for (regno = 0; regno < 16; regno++) {
308 cmap[(regno * 2) + 1] = regno & 0x0f;
311 #endif /* LCD_MONOCHROME */
313 /*----------------------------------------------------------------------*/
314 void lcd_enable (void)
318 /*----------------------------------------------------------------------*/
319 #ifdef NOT_USED_SO_FAR
320 static void lcd_disable (void)
323 #endif /* NOT_USED_SO_FAR */
325 /*----------------------------------------------------------------------*/
327 /************************************************************************/
328 /* ** PXA255 specific routines */
329 /************************************************************************/
332 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
333 * descriptors and palette areas.
335 ulong calc_fbsize (void)
338 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
340 size = line_length * panel_info.vl_row;
346 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
348 u_long palette_mem_size;
349 struct pxafb_info *fbi = &vid->pxa;
350 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
352 fbi->screen = (u_long)lcdbase;
354 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
355 palette_mem_size = fbi->palette_size * sizeof(u16);
357 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
358 /* locate palette and descs at end of page following fb */
359 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
363 #ifdef CONFIG_CPU_MONAHANS
364 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
366 static void pxafb_setup_gpio (vidinfo_t *vid)
371 * setup is based on type of panel supported
374 lccr0 = vid->pxa.reg_lccr0;
376 /* 4 bit interface */
377 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
379 debug("Setting GPIO for 4 bit data\n");
381 writel(readl(GPDR1) | (0xf << 26), GPDR1);
382 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
386 writel(readl(GPDR2) | (0xf << 10), GPDR2);
387 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
391 /* 8 bit interface */
392 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
393 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
395 debug("Setting GPIO for 8 bit data\n");
397 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
398 writel(readl(GPDR2) | (0x3), GPDR2);
400 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
402 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
405 writel(readl(GPDR2) | (0xf << 10), GPDR2);
406 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
410 /* 16 bit interface */
411 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
413 debug("Setting GPIO for 16 bit data\n");
415 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
416 writel(readl(GPDR2) | 0x00003fff, GPDR2);
418 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
420 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
424 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
429 static void pxafb_enable_controller (vidinfo_t *vid)
431 debug("Enabling LCD controller\n");
433 /* Sequence from 11.7.10 */
434 writel(vid->pxa.reg_lccr3, LCCR3);
435 writel(vid->pxa.reg_lccr2, LCCR2);
436 writel(vid->pxa.reg_lccr1, LCCR1);
437 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
438 writel(vid->pxa.fdadr0, FDADR0);
439 writel(vid->pxa.fdadr1, FDADR1);
440 writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
442 #ifdef CONFIG_CPU_MONAHANS
443 writel(readl(CKENA) | CKENA_1_LCD, CKENA);
445 writel(readl(CKEN) | CKEN16_LCD, CKEN);
448 debug("FDADR0 = 0x%08x\n", readl(FDADR0));
449 debug("FDADR1 = 0x%08x\n", readl(FDADR1));
450 debug("LCCR0 = 0x%08x\n", readl(LCCR0));
451 debug("LCCR1 = 0x%08x\n", readl(LCCR1));
452 debug("LCCR2 = 0x%08x\n", readl(LCCR2));
453 debug("LCCR3 = 0x%08x\n", readl(LCCR3));
456 static int pxafb_init (vidinfo_t *vid)
458 struct pxafb_info *fbi = &vid->pxa;
460 debug("Configuring PXA LCD\n");
462 fbi->reg_lccr0 = REG_LCCR0;
463 fbi->reg_lccr3 = REG_LCCR3;
465 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
466 vid->vl_col, vid->vl_hpw,
467 vid->vl_blw, vid->vl_elw);
468 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
469 vid->vl_row, vid->vl_vpw,
470 vid->vl_bfw, vid->vl_efw);
473 LCCR1_DisWdth(vid->vl_col) +
474 LCCR1_HorSnchWdth(vid->vl_hpw) +
475 LCCR1_BegLnDel(vid->vl_blw) +
476 LCCR1_EndLnDel(vid->vl_elw);
479 LCCR2_DisHght(vid->vl_row) +
480 LCCR2_VrtSnchWdth(vid->vl_vpw) +
481 LCCR2_BegFrmDel(vid->vl_bfw) +
482 LCCR2_EndFrmDel(vid->vl_efw);
484 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
485 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
486 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
489 /* setup dma descriptors */
490 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
491 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
492 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
494 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
495 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
496 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
498 /* populate descriptors */
499 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
500 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
501 fbi->dmadesc_fblow->fidr = 0;
502 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
504 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
506 fbi->dmadesc_fbhigh->fsadr = fbi->screen;
507 fbi->dmadesc_fbhigh->fidr = 0;
508 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
510 fbi->dmadesc_palette->fsadr = fbi->palette;
511 fbi->dmadesc_palette->fidr = 0;
512 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
514 if( NBITS(vid->vl_bpix) < 12)
516 /* assume any mode with <12 bpp is palette driven */
517 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
518 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
519 /* flips back and forth between pal and fbhigh */
520 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
524 /* palette shouldn't be loaded in true-color mode */
525 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
526 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
529 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
530 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
531 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
533 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
534 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
535 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
537 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
538 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
539 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
541 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
542 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
543 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
548 /************************************************************************/
549 /************************************************************************/
551 #endif /* CONFIG_LCD */