git.sur5r.net Git - u-boot/blob - arch/arm/cpu/pxa/pxafb.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************/
  27 /* ** HEADER FILES                                                      */
  28 /************************************************************************/
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <version.h>
  33 #include <stdarg.h>
  34 #include <linux/types.h>
  35 #include <stdio_dev.h>
  36 #include <lcd.h>
  37 #include <asm/arch/pxa-regs.h>
  38 #include <asm/io.h>
  39
  40 /* #define DEBUG */
  41
  42 #ifdef CONFIG_LCD
  43
  44 /*----------------------------------------------------------------------*/
  45 /*
  46  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  47  * your display.
  48  */
  49
  50 #ifdef CONFIG_PXA_VGA
  51 /* LCD outputs connected to a video DAC  */
  52 # define LCD_BPP        LCD_COLOR8
  53
  54 /* you have to set lccr0 and lccr3 (including pcd) */
  55 # define REG_LCCR0      0x003008f8
  56 # define REG_LCCR3      0x0300FF01
  57
  58 /* 640x480x16 @ 61 Hz */
  59 vidinfo_t panel_info = {
  60         .vl_col         = 640,
  61         .vl_row         = 480,
  62         .vl_width       = 640,
  63         .vl_height      = 480,
  64         .vl_clkp        = CONFIG_SYS_HIGH,
  65         .vl_oep         = CONFIG_SYS_HIGH,
  66         .vl_hsp         = CONFIG_SYS_HIGH,
  67         .vl_vsp         = CONFIG_SYS_HIGH,
  68         .vl_dp          = CONFIG_SYS_HIGH,
  69         .vl_bpix        = LCD_BPP,
  70         .vl_lbw         = 0,
  71         .vl_splt        = 0,
  72         .vl_clor        = 0,
  73         .vl_tft         = 1,
  74         .vl_hpw         = 40,
  75         .vl_blw         = 56,
  76         .vl_elw         = 56,
  77         .vl_vpw         = 20,
  78         .vl_bfw         = 8,
  79         .vl_efw         = 8,
  80 };
  81 #endif /* CONFIG_PXA_VIDEO */
  82
  83 /*----------------------------------------------------------------------*/
  84 #ifdef CONFIG_SHARP_LM8V31
  85
  86 # define LCD_BPP        LCD_COLOR8
  87 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  88
  89 /* you have to set lccr0 and lccr3 (including pcd) */
  90 # define REG_LCCR0      0x0030087C
  91 # define REG_LCCR3      0x0340FF08
  92
  93 vidinfo_t panel_info = {
  94         .vl_col         = 640,
  95         .vl_row         = 480,
  96         .vl_width       = 157,
  97         .vl_height      = 118,
  98         .vl_clkp        = CONFIG_SYS_HIGH,
  99         .vl_oep         = CONFIG_SYS_HIGH,
 100         .vl_hsp         = CONFIG_SYS_HIGH,
 101         .vl_vsp         = CONFIG_SYS_HIGH,
 102         .vl_dp          = CONFIG_SYS_HIGH,
 103         .vl_bpix        = LCD_BPP,
 104         .vl_lbw         = 0,
 105         .vl_splt        = 1,
 106         .vl_clor        = 1,
 107         .vl_tft         = 0,
 108         .vl_hpw         = 1,
 109         .vl_blw         = 3,
 110         .vl_elw         = 3,
 111         .vl_vpw         = 1,
 112         .vl_bfw         = 0,
 113         .vl_efw         = 0,
 114 };
 115 #endif /* CONFIG_SHARP_LM8V31 */
 116 /*----------------------------------------------------------------------*/
 117 #ifdef CONFIG_VOIPAC_LCD
 118
 119 # define LCD_BPP        LCD_COLOR8
 120 # define LCD_INVERT_COLORS
 121
 122 /* you have to set lccr0 and lccr3 (including pcd) */
 123 # define REG_LCCR0      0x043008f8
 124 # define REG_LCCR3      0x0340FF08
 125
 126 vidinfo_t panel_info = {
 127         .vl_col         = 640,
 128         .vl_row         = 480,
 129         .vl_width       = 157,
 130         .vl_height      = 118,
 131         .vl_clkp        = CONFIG_SYS_HIGH,
 132         .vl_oep         = CONFIG_SYS_HIGH,
 133         .vl_hsp         = CONFIG_SYS_HIGH,
 134         .vl_vsp         = CONFIG_SYS_HIGH,
 135         .vl_dp          = CONFIG_SYS_HIGH,
 136         .vl_bpix        = LCD_BPP,
 137         .vl_lbw         = 0,
 138         .vl_splt        = 1,
 139         .vl_clor        = 1,
 140         .vl_tft         = 1,
 141         .vl_hpw         = 32,
 142         .vl_blw         = 144,
 143         .vl_elw         = 32,
 144         .vl_vpw         = 2,
 145         .vl_bfw         = 13,
 146         .vl_efw         = 30,
 147 };
 148 #endif /* CONFIG_VOIPAC_LCD */
 149
 150 /*----------------------------------------------------------------------*/
 151 #ifdef CONFIG_HITACHI_SX14
 152 /* Hitachi SX14Q004-ZZA color STN LCD */
 153 #define LCD_BPP         LCD_COLOR8
 154
 155 /* you have to set lccr0 and lccr3 (including pcd) */
 156 #define REG_LCCR0       0x00301079
 157 #define REG_LCCR3       0x0340FF20
 158
 159 vidinfo_t panel_info = {
 160         .vl_col         = 320,
 161         .vl_row         = 240,
 162         .vl_width       = 167,
 163         .vl_height      = 109,
 164         .vl_clkp        = CONFIG_SYS_HIGH,
 165         .vl_oep         = CONFIG_SYS_HIGH,
 166         .vl_hsp         = CONFIG_SYS_HIGH,
 167         .vl_vsp         = CONFIG_SYS_HIGH,
 168         .vl_dp          = CONFIG_SYS_HIGH,
 169         .vl_bpix        = LCD_BPP,
 170         .vl_lbw         = 1,
 171         .vl_splt        = 0,
 172         .vl_clor        = 1,
 173         .vl_tft         = 0,
 174         .vl_hpw         = 1,
 175         .vl_blw         = 1,
 176         .vl_elw         = 1,
 177         .vl_vpw         = 7,
 178         .vl_bfw         = 0,
 179         .vl_efw         = 0,
 180 };
 181 #endif /* CONFIG_HITACHI_SX14 */
 182
 183 /*----------------------------------------------------------------------*/
 184 #ifdef CONFIG_LMS283GF05
 185
 186 # define LCD_BPP        LCD_COLOR8
 187 /*# define LCD_INVERT_COLORS*/
 188
 189 /* you have to set lccr0 and lccr3 (including pcd) */
 190 # define REG_LCCR0      0x043008f8
 191 # define REG_LCCR3      0x03b00009
 192
 193 vidinfo_t panel_info = {
 194         .vl_col         = 240,
 195         .vl_row         = 320,
 196         .vl_width       = 240,
 197         .vl_height      = 320,
 198         .vl_clkp        = CONFIG_SYS_HIGH,
 199         .vl_oep         = CONFIG_SYS_LOW,
 200         .vl_hsp         = CONFIG_SYS_LOW,
 201         .vl_vsp         = CONFIG_SYS_LOW,
 202         .vl_dp          = CONFIG_SYS_HIGH,
 203         .vl_bpix        = LCD_BPP,
 204         .vl_lbw         = 0,
 205         .vl_splt        = 1,
 206         .vl_clor        = 1,
 207         .vl_tft         = 1,
 208         .vl_hpw         = 4,
 209         .vl_blw         = 4,
 210         .vl_elw         = 8,
 211         .vl_vpw         = 4,
 212         .vl_bfw         = 4,
 213         .vl_efw         = 8,
 214 };
 215 #endif /* CONFIG_LMS283GF05 */
 216
 217 /*----------------------------------------------------------------------*/
 218
 219 #ifdef CONFIG_ACX517AKN
 220
 221 # define LCD_BPP        LCD_COLOR8
 222
 223 /* you have to set lccr0 and lccr3 (including pcd) */
 224 # define REG_LCCR0      0x003008f9
 225 # define REG_LCCR3      0x03700006
 226
 227 vidinfo_t panel_info = {
 228         .vl_col         = 320,
 229         .vl_row         = 320,
 230         .vl_width       = 320,
 231         .vl_height      = 320,
 232         .vl_clkp        = CONFIG_SYS_HIGH,
 233         .vl_oep         = CONFIG_SYS_LOW,
 234         .vl_hsp         = CONFIG_SYS_LOW,
 235         .vl_vsp         = CONFIG_SYS_LOW,
 236         .vl_dp          = CONFIG_SYS_HIGH,
 237         .vl_bpix        = LCD_BPP,
 238         .vl_lbw         = 0,
 239         .vl_splt        = 1,
 240         .vl_clor        = 1,
 241         .vl_tft         = 1,
 242         .vl_hpw         = 0x04,
 243         .vl_blw         = 0x1c,
 244         .vl_elw         = 0x08,
 245         .vl_vpw         = 0x01,
 246         .vl_bfw         = 0x07,
 247         .vl_efw         = 0x08,
 248 };
 249 #endif /* CONFIG_ACX517AKN */
 250
 251 /*----------------------------------------------------------------------*/
 252
 253 #ifdef CONFIG_LQ038J7DH53
 254
 255 # define LCD_BPP        LCD_COLOR8
 256
 257 /* you have to set lccr0 and lccr3 (including pcd) */
 258 # define REG_LCCR0      0x003008f9
 259 # define REG_LCCR3      0x03700004
 260
 261 vidinfo_t panel_info = {
 262         .vl_col         = 320,
 263         .vl_row         = 480,
 264         .vl_width       = 320,
 265         .vl_height      = 480,
 266         .vl_clkp        = CONFIG_SYS_HIGH,
 267         .vl_oep         = CONFIG_SYS_LOW,
 268         .vl_hsp         = CONFIG_SYS_LOW,
 269         .vl_vsp         = CONFIG_SYS_LOW,
 270         .vl_dp          = CONFIG_SYS_HIGH,
 271         .vl_bpix        = LCD_BPP,
 272         .vl_lbw         = 0,
 273         .vl_splt        = 1,
 274         .vl_clor        = 1,
 275         .vl_tft         = 1,
 276         .vl_hpw         = 0x04,
 277         .vl_blw         = 0x20,
 278         .vl_elw         = 0x01,
 279         .vl_vpw         = 0x01,
 280         .vl_bfw         = 0x04,
 281         .vl_efw         = 0x01,
 282 };
 283 #endif /* CONFIG_ACX517AKN */
 284
 285 /*----------------------------------------------------------------------*/
 286
 287 #if LCD_BPP == LCD_COLOR8
 288 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 289 #endif
 290 #if LCD_BPP == LCD_MONOCHROME
 291 void lcd_initcolregs (void);
 292 #endif
 293
 294 #ifdef NOT_USED_SO_FAR
 295 void lcd_disable (void);
 296 void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
 297 #endif /* NOT_USED_SO_FAR */
 298
 299 void lcd_ctrl_init      (void *lcdbase);
 300 void lcd_enable (void);
 301
 302 int lcd_line_length;
 303 int lcd_color_fg;
 304 int lcd_color_bg;
 305
 306 void *lcd_base;                 /* Start of framebuffer memory  */
 307 void *lcd_console_address;              /* Start of console buffer      */
 308
 309 short console_col;
 310 short console_row;
 311
 312 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 313 static void pxafb_setup_gpio (vidinfo_t *vid);
 314 static void pxafb_enable_controller (vidinfo_t *vid);
 315 static int pxafb_init (vidinfo_t *vid);
 316 /************************************************************************/
 317
 318 /************************************************************************/
 319 /* ---------------  PXA chipset specific functions  ------------------- */
 320 /************************************************************************/
 321
 322 void lcd_ctrl_init (void *lcdbase)
 323 {
 324         pxafb_init_mem(lcdbase, &panel_info);
 325         pxafb_init(&panel_info);
 326         pxafb_setup_gpio(&panel_info);
 327         pxafb_enable_controller(&panel_info);
 328 }
 329
 330 /*----------------------------------------------------------------------*/
 331 #ifdef NOT_USED_SO_FAR
 332 void
 333 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
 334 {
 335 }
 336 #endif /* NOT_USED_SO_FAR */
 337
 338 /*----------------------------------------------------------------------*/
 339 #if LCD_BPP == LCD_COLOR8
 340 void
 341 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 342 {
 343         struct pxafb_info *fbi = &panel_info.pxa;
 344         unsigned short *palette = (unsigned short *)fbi->palette;
 345         u_int val;
 346
 347         if (regno < fbi->palette_size) {
 348                 val = ((red << 8) & 0xf800);
 349                 val |= ((green << 4) & 0x07e0);
 350                 val |= (blue & 0x001f);
 351
 352 #ifdef LCD_INVERT_COLORS
 353                 palette[regno] = ~val;
 354 #else
 355                 palette[regno] = val;
 356 #endif
 357         }
 358
 359         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 360                 regno, &palette[regno],
 361                 red, green, blue,
 362                 palette[regno]);
 363 }
 364 #endif /* LCD_COLOR8 */
 365
 366 /*----------------------------------------------------------------------*/
 367 #if LCD_BPP == LCD_MONOCHROME
 368 void lcd_initcolregs (void)
 369 {
 370         struct pxafb_info *fbi = &panel_info.pxa;
 371         cmap = (ushort *)fbi->palette;
 372         ushort regno;
 373
 374         for (regno = 0; regno < 16; regno++) {
 375                 cmap[regno * 2] = 0;
 376                 cmap[(regno * 2) + 1] = regno & 0x0f;
 377         }
 378 }
 379 #endif /* LCD_MONOCHROME */
 380
 381 /*----------------------------------------------------------------------*/
 382 void lcd_enable (void)
 383 {
 384 }
 385
 386 /*----------------------------------------------------------------------*/
 387 #ifdef  NOT_USED_SO_FAR
 388 static void lcd_disable (void)
 389 {
 390 }
 391 #endif /* NOT_USED_SO_FAR */
 392
 393 /*----------------------------------------------------------------------*/
 394
 395 /************************************************************************/
 396 /* ** PXA255 specific routines                                          */
 397 /************************************************************************/
 398
 399 /*
 400  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 401  * descriptors and palette areas.
 402  */
 403 ulong calc_fbsize (void)
 404 {
 405         ulong size;
 406         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 407
 408         size = line_length * panel_info.vl_row;
 409         size += PAGE_SIZE;
 410
 411         return size;
 412 }
 413
 414 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 415 {
 416         u_long palette_mem_size;
 417         struct pxafb_info *fbi = &vid->pxa;
 418         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 419
 420         fbi->screen = (u_long)lcdbase;
 421
 422         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 423         palette_mem_size = fbi->palette_size * sizeof(u16);
 424
 425         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 426         /* locate palette and descs at end of page following fb */
 427         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 428
 429         return 0;
 430 }
 431 #ifdef  CONFIG_CPU_MONAHANS
 432 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 433 #else
 434 static void pxafb_setup_gpio (vidinfo_t *vid)
 435 {
 436         u_long lccr0;
 437
 438         /*
 439          * setup is based on type of panel supported
 440          */
 441
 442         lccr0 = vid->pxa.reg_lccr0;
 443
 444         /* 4 bit interface */
 445         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 446         {
 447                 debug("Setting GPIO for 4 bit data\n");
 448                 /* bits 58-61 */
 449                 writel(readl(GPDR1) | (0xf << 26), GPDR1);
 450                 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
 451                         GAFR1_U);
 452
 453                 /* bits 74-77 */
 454                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 455                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 456                         GAFR2_L);
 457         }
 458
 459         /* 8 bit interface */
 460         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 461                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 462         {
 463                 debug("Setting GPIO for 8 bit data\n");
 464                 /* bits 58-65 */
 465                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 466                 writel(readl(GPDR2) | (0x3), GPDR2);
 467
 468                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 469                         GAFR1_U);
 470                 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 471
 472                 /* bits 74-77 */
 473                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 474                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 475                         GAFR2_L);
 476         }
 477
 478         /* 16 bit interface */
 479         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 480         {
 481                 debug("Setting GPIO for 16 bit data\n");
 482                 /* bits 58-77 */
 483                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 484                 writel(readl(GPDR2) | 0x00003fff, GPDR2);
 485
 486                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 487                         GAFR1_U);
 488                 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 489         }
 490         else
 491         {
 492                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 493         }
 494 }
 495 #endif
 496
 497 static void pxafb_enable_controller (vidinfo_t *vid)
 498 {
 499         debug("Enabling LCD controller\n");
 500
 501         /* Sequence from 11.7.10 */
 502         writel(vid->pxa.reg_lccr3, LCCR3);
 503         writel(vid->pxa.reg_lccr2, LCCR2);
 504         writel(vid->pxa.reg_lccr1, LCCR1);
 505         writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
 506         writel(vid->pxa.fdadr0, FDADR0);
 507         writel(vid->pxa.fdadr1, FDADR1);
 508         writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 509
 510 #ifdef  CONFIG_CPU_MONAHANS
 511         writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 512 #else
 513         writel(readl(CKEN) | CKEN16_LCD, CKEN);
 514 #endif
 515
 516         debug("FDADR0 = 0x%08x\n", readl(FDADR0));
 517         debug("FDADR1 = 0x%08x\n", readl(FDADR1));
 518         debug("LCCR0 = 0x%08x\n", readl(LCCR0));
 519         debug("LCCR1 = 0x%08x\n", readl(LCCR1));
 520         debug("LCCR2 = 0x%08x\n", readl(LCCR2));
 521         debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 522 }
 523
 524 static int pxafb_init (vidinfo_t *vid)
 525 {
 526         struct pxafb_info *fbi = &vid->pxa;
 527
 528         debug("Configuring PXA LCD\n");
 529
 530         fbi->reg_lccr0 = REG_LCCR0;
 531         fbi->reg_lccr3 = REG_LCCR3;
 532
 533         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 534                 vid->vl_col, vid->vl_hpw,
 535                 vid->vl_blw, vid->vl_elw);
 536         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 537                 vid->vl_row, vid->vl_vpw,
 538                 vid->vl_bfw, vid->vl_efw);
 539
 540         fbi->reg_lccr1 =
 541                 LCCR1_DisWdth(vid->vl_col) +
 542                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 543                 LCCR1_BegLnDel(vid->vl_blw) +
 544                 LCCR1_EndLnDel(vid->vl_elw);
 545
 546         fbi->reg_lccr2 =
 547                 LCCR2_DisHght(vid->vl_row) +
 548                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 549                 LCCR2_BegFrmDel(vid->vl_bfw) +
 550                 LCCR2_EndFrmDel(vid->vl_efw);
 551
 552         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 553         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 554                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 555
 556
 557         /* setup dma descriptors */
 558         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 559         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 560         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 561
 562         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 563                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 564                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 565
 566         /* populate descriptors */
 567         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 568         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 569         fbi->dmadesc_fblow->fidr  = 0;
 570         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 571
 572         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 573
 574         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 575         fbi->dmadesc_fbhigh->fidr = 0;
 576         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 577
 578         fbi->dmadesc_palette->fsadr = fbi->palette;
 579         fbi->dmadesc_palette->fidr  = 0;
 580         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 581
 582         if( NBITS(vid->vl_bpix) < 12)
 583         {
 584                 /* assume any mode with <12 bpp is palette driven */
 585                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 586                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 587                 /* flips back and forth between pal and fbhigh */
 588                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 589         }
 590         else
 591         {
 592                 /* palette shouldn't be loaded in true-color mode */
 593                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 594                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 595         }
 596
 597         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 598         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 599         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 600
 601         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 602         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 603         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 604
 605         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 606         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 607         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 608
 609         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 610         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 611         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 612
 613         return 0;
 614 }
 615
 616 /************************************************************************/
 617 /************************************************************************/
 618
 619 #endif /* CONFIG_LCD */