git.sur5r.net Git - u-boot/blob - arch/arm/cpu/pxa/pxafb.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************/
  27 /* ** HEADER FILES                                                      */
  28 /************************************************************************/
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <version.h>
  33 #include <stdarg.h>
  34 #include <linux/types.h>
  35 #include <stdio_dev.h>
  36 #include <lcd.h>
  37 #include <asm/arch/pxa-regs.h>
  38
  39 /* #define DEBUG */
  40
  41 #ifdef CONFIG_LCD
  42
  43 /*----------------------------------------------------------------------*/
  44 /*
  45  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  46  * your display.
  47  */
  48
  49 #ifdef CONFIG_PXA_VGA
  50 /* LCD outputs connected to a video DAC  */
  51 # define LCD_BPP        LCD_COLOR8
  52
  53 /* you have to set lccr0 and lccr3 (including pcd) */
  54 # define REG_LCCR0      0x003008f8
  55 # define REG_LCCR3      0x0300FF01
  56
  57 /* 640x480x16 @ 61 Hz */
  58 vidinfo_t panel_info = {
  59         vl_col:         640,
  60         vl_row:         480,
  61         vl_width:       640,
  62         vl_height:      480,
  63         vl_clkp:        CONFIG_SYS_HIGH,
  64         vl_oep:         CONFIG_SYS_HIGH,
  65         vl_hsp:         CONFIG_SYS_HIGH,
  66         vl_vsp:         CONFIG_SYS_HIGH,
  67         vl_dp:          CONFIG_SYS_HIGH,
  68         vl_bpix:        LCD_BPP,
  69         vl_lbw:         0,
  70         vl_splt:        0,
  71         vl_clor:        0,
  72         vl_tft:         1,
  73         vl_hpw:         40,
  74         vl_blw:         56,
  75         vl_elw:         56,
  76         vl_vpw:         20,
  77         vl_bfw:         8,
  78         vl_efw:         8,
  79 };
  80 #endif /* CONFIG_PXA_VIDEO */
  81
  82 /*----------------------------------------------------------------------*/
  83 #ifdef CONFIG_SHARP_LM8V31
  84
  85 # define LCD_BPP        LCD_COLOR8
  86 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  87
  88 /* you have to set lccr0 and lccr3 (including pcd) */
  89 # define REG_LCCR0      0x0030087C
  90 # define REG_LCCR3      0x0340FF08
  91
  92 vidinfo_t panel_info = {
  93         vl_col:         640,
  94         vl_row:         480,
  95         vl_width:       157,
  96         vl_height:      118,
  97         vl_clkp:        CONFIG_SYS_HIGH,
  98         vl_oep:         CONFIG_SYS_HIGH,
  99         vl_hsp:         CONFIG_SYS_HIGH,
 100         vl_vsp:         CONFIG_SYS_HIGH,
 101         vl_dp:          CONFIG_SYS_HIGH,
 102         vl_bpix:        LCD_BPP,
 103         vl_lbw:         0,
 104         vl_splt:        1,
 105         vl_clor:        1,
 106         vl_tft:         0,
 107         vl_hpw:         1,
 108         vl_blw:         3,
 109         vl_elw:         3,
 110         vl_vpw:         1,
 111         vl_bfw:         0,
 112         vl_efw:         0,
 113 };
 114 #endif /* CONFIG_SHARP_LM8V31 */
 115 /*----------------------------------------------------------------------*/
 116 #ifdef CONFIG_VOIPAC_LCD
 117
 118 # define LCD_BPP        LCD_COLOR8
 119 # define LCD_INVERT_COLORS
 120
 121 /* you have to set lccr0 and lccr3 (including pcd) */
 122 # define REG_LCCR0      0x043008f8
 123 # define REG_LCCR3      0x0340FF08
 124
 125 vidinfo_t panel_info = {
 126         vl_col:         640,
 127         vl_row:         480,
 128         vl_width:       157,
 129         vl_height:      118,
 130         vl_clkp:        CONFIG_SYS_HIGH,
 131         vl_oep:         CONFIG_SYS_HIGH,
 132         vl_hsp:         CONFIG_SYS_HIGH,
 133         vl_vsp:         CONFIG_SYS_HIGH,
 134         vl_dp:          CONFIG_SYS_HIGH,
 135         vl_bpix:        LCD_BPP,
 136         vl_lbw:         0,
 137         vl_splt:        1,
 138         vl_clor:        1,
 139         vl_tft:         1,
 140         vl_hpw:         32,
 141         vl_blw:         144,
 142         vl_elw:         32,
 143         vl_vpw:         2,
 144         vl_bfw:         13,
 145         vl_efw:         30,
 146 };
 147 #endif /* CONFIG_VOIPAC_LCD */
 148
 149 /*----------------------------------------------------------------------*/
 150 #ifdef CONFIG_HITACHI_SX14
 151 /* Hitachi SX14Q004-ZZA color STN LCD */
 152 #define LCD_BPP         LCD_COLOR8
 153
 154 /* you have to set lccr0 and lccr3 (including pcd) */
 155 #define REG_LCCR0       0x00301079
 156 #define REG_LCCR3       0x0340FF20
 157
 158 vidinfo_t panel_info = {
 159         vl_col:         320,
 160         vl_row:         240,
 161         vl_width:       167,
 162         vl_height:      109,
 163         vl_clkp:        CONFIG_SYS_HIGH,
 164         vl_oep:         CONFIG_SYS_HIGH,
 165         vl_hsp:         CONFIG_SYS_HIGH,
 166         vl_vsp:         CONFIG_SYS_HIGH,
 167         vl_dp:          CONFIG_SYS_HIGH,
 168         vl_bpix:        LCD_BPP,
 169         vl_lbw:         1,
 170         vl_splt:        0,
 171         vl_clor:        1,
 172         vl_tft:         0,
 173         vl_hpw:         1,
 174         vl_blw:         1,
 175         vl_elw:         1,
 176         vl_vpw:         7,
 177         vl_bfw:         0,
 178         vl_efw:         0,
 179 };
 180 #endif /* CONFIG_HITACHI_SX14 */
 181
 182 /*----------------------------------------------------------------------*/
 183
 184 #if LCD_BPP == LCD_COLOR8
 185 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 186 #endif
 187 #if LCD_BPP == LCD_MONOCHROME
 188 void lcd_initcolregs (void);
 189 #endif
 190
 191 #ifdef NOT_USED_SO_FAR
 192 void lcd_disable (void);
 193 void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
 194 #endif /* NOT_USED_SO_FAR */
 195
 196 void lcd_ctrl_init      (void *lcdbase);
 197 void lcd_enable (void);
 198
 199 int lcd_line_length;
 200 int lcd_color_fg;
 201 int lcd_color_bg;
 202
 203 void *lcd_base;                 /* Start of framebuffer memory  */
 204 void *lcd_console_address;              /* Start of console buffer      */
 205
 206 short console_col;
 207 short console_row;
 208
 209 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 210 static void pxafb_setup_gpio (vidinfo_t *vid);
 211 static void pxafb_enable_controller (vidinfo_t *vid);
 212 static int pxafb_init (vidinfo_t *vid);
 213 /************************************************************************/
 214
 215 /************************************************************************/
 216 /* ---------------  PXA chipset specific functions  ------------------- */
 217 /************************************************************************/
 218
 219 void lcd_ctrl_init (void *lcdbase)
 220 {
 221         pxafb_init_mem(lcdbase, &panel_info);
 222         pxafb_init(&panel_info);
 223         pxafb_setup_gpio(&panel_info);
 224         pxafb_enable_controller(&panel_info);
 225 }
 226
 227 /*----------------------------------------------------------------------*/
 228 #ifdef NOT_USED_SO_FAR
 229 void
 230 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
 231 {
 232 }
 233 #endif /* NOT_USED_SO_FAR */
 234
 235 /*----------------------------------------------------------------------*/
 236 #if LCD_BPP == LCD_COLOR8
 237 void
 238 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 239 {
 240         struct pxafb_info *fbi = &panel_info.pxa;
 241         unsigned short *palette = (unsigned short *)fbi->palette;
 242         u_int val;
 243
 244         if (regno < fbi->palette_size) {
 245                 val = ((red << 8) & 0xf800);
 246                 val |= ((green << 4) & 0x07e0);
 247                 val |= (blue & 0x001f);
 248
 249 #ifdef LCD_INVERT_COLORS
 250                 palette[regno] = ~val;
 251 #else
 252                 palette[regno] = val;
 253 #endif
 254         }
 255
 256         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 257                 regno, &palette[regno],
 258                 red, green, blue,
 259                 palette[regno]);
 260 }
 261 #endif /* LCD_COLOR8 */
 262
 263 /*----------------------------------------------------------------------*/
 264 #if LCD_BPP == LCD_MONOCHROME
 265 void lcd_initcolregs (void)
 266 {
 267         struct pxafb_info *fbi = &panel_info.pxa;
 268         cmap = (ushort *)fbi->palette;
 269         ushort regno;
 270
 271         for (regno = 0; regno < 16; regno++) {
 272                 cmap[regno * 2] = 0;
 273                 cmap[(regno * 2) + 1] = regno & 0x0f;
 274         }
 275 }
 276 #endif /* LCD_MONOCHROME */
 277
 278 /*----------------------------------------------------------------------*/
 279 void lcd_enable (void)
 280 {
 281 }
 282
 283 /*----------------------------------------------------------------------*/
 284 #ifdef  NOT_USED_SO_FAR
 285 static void lcd_disable (void)
 286 {
 287 }
 288 #endif /* NOT_USED_SO_FAR */
 289
 290 /*----------------------------------------------------------------------*/
 291
 292 /************************************************************************/
 293 /* ** PXA255 specific routines                                          */
 294 /************************************************************************/
 295
 296 /*
 297  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 298  * descriptors and palette areas.
 299  */
 300 ulong calc_fbsize (void)
 301 {
 302         ulong size;
 303         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 304
 305         size = line_length * panel_info.vl_row;
 306         size += PAGE_SIZE;
 307
 308         return size;
 309 }
 310
 311 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 312 {
 313         u_long palette_mem_size;
 314         struct pxafb_info *fbi = &vid->pxa;
 315         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 316
 317         fbi->screen = (u_long)lcdbase;
 318
 319         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 320         palette_mem_size = fbi->palette_size * sizeof(u16);
 321
 322         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 323         /* locate palette and descs at end of page following fb */
 324         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 325
 326         return 0;
 327 }
 328 #ifdef  CONFIG_CPU_MONAHANS
 329 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 330 #else
 331 static void pxafb_setup_gpio (vidinfo_t *vid)
 332 {
 333         u_long lccr0;
 334
 335         /*
 336          * setup is based on type of panel supported
 337          */
 338
 339         lccr0 = vid->pxa.reg_lccr0;
 340
 341         /* 4 bit interface */
 342         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 343         {
 344                 debug("Setting GPIO for 4 bit data\n");
 345                 /* bits 58-61 */
 346                 GPDR1 |= (0xf << 26);
 347                 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
 348
 349                 /* bits 74-77 */
 350                 GPDR2 |= (0xf << 10);
 351                 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
 352         }
 353
 354         /* 8 bit interface */
 355         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 356                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 357         {
 358                 debug("Setting GPIO for 8 bit data\n");
 359                 /* bits 58-65 */
 360                 GPDR1 |= (0x3f << 26);
 361                 GPDR2 |= (0x3);
 362
 363                 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
 364                 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
 365
 366                 /* bits 74-77 */
 367                 GPDR2 |= (0xf << 10);
 368                 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
 369         }
 370
 371         /* 16 bit interface */
 372         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 373         {
 374                 debug("Setting GPIO for 16 bit data\n");
 375                 /* bits 58-77 */
 376                 GPDR1 |= (0x3f << 26);
 377                 GPDR2 |= 0x00003fff;
 378
 379                 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
 380                 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
 381         }
 382         else
 383         {
 384                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 385         }
 386 }
 387 #endif
 388
 389 static void pxafb_enable_controller (vidinfo_t *vid)
 390 {
 391         debug("Enabling LCD controller\n");
 392
 393         /* Sequence from 11.7.10 */
 394         LCCR3  = vid->pxa.reg_lccr3;
 395         LCCR2  = vid->pxa.reg_lccr2;
 396         LCCR1  = vid->pxa.reg_lccr1;
 397         LCCR0  = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
 398         FDADR0 = vid->pxa.fdadr0;
 399         FDADR1 = vid->pxa.fdadr1;
 400         LCCR0 |= LCCR0_ENB;
 401
 402 #ifdef  CONFIG_CPU_MONAHANS
 403         CKENA |= CKENA_1_LCD;
 404 #else
 405         CKEN |= CKEN16_LCD;
 406 #endif
 407
 408         debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
 409         debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
 410         debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
 411         debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
 412         debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
 413         debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
 414 }
 415
 416 static int pxafb_init (vidinfo_t *vid)
 417 {
 418         struct pxafb_info *fbi = &vid->pxa;
 419
 420         debug("Configuring PXA LCD\n");
 421
 422         fbi->reg_lccr0 = REG_LCCR0;
 423         fbi->reg_lccr3 = REG_LCCR3;
 424
 425         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 426                 vid->vl_col, vid->vl_hpw,
 427                 vid->vl_blw, vid->vl_elw);
 428         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 429                 vid->vl_row, vid->vl_vpw,
 430                 vid->vl_bfw, vid->vl_efw);
 431
 432         fbi->reg_lccr1 =
 433                 LCCR1_DisWdth(vid->vl_col) +
 434                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 435                 LCCR1_BegLnDel(vid->vl_blw) +
 436                 LCCR1_EndLnDel(vid->vl_elw);
 437
 438         fbi->reg_lccr2 =
 439                 LCCR2_DisHght(vid->vl_row) +
 440                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 441                 LCCR2_BegFrmDel(vid->vl_bfw) +
 442                 LCCR2_EndFrmDel(vid->vl_efw);
 443
 444         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 445         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 446                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 447
 448
 449         /* setup dma descriptors */
 450         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 451         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 452         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 453
 454         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 455                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 456                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 457
 458         /* populate descriptors */
 459         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 460         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 461         fbi->dmadesc_fblow->fidr  = 0;
 462         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 463
 464         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 465
 466         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 467         fbi->dmadesc_fbhigh->fidr = 0;
 468         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 469
 470         fbi->dmadesc_palette->fsadr = fbi->palette;
 471         fbi->dmadesc_palette->fidr  = 0;
 472         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 473
 474         if( NBITS(vid->vl_bpix) < 12)
 475         {
 476                 /* assume any mode with <12 bpp is palette driven */
 477                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 478                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 479                 /* flips back and forth between pal and fbhigh */
 480                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 481         }
 482         else
 483         {
 484                 /* palette shouldn't be loaded in true-color mode */
 485                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 486                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 487         }
 488
 489         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 490         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 491         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 492
 493         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 494         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 495         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 496
 497         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 498         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 499         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 500
 501         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 502         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 503         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 504
 505         return 0;
 506 }
 507
 508 /************************************************************************/
 509 /************************************************************************/
 510
 511 #endif /* CONFIG_LCD */