2 * armboot - Startup Code for XScale CPU-core
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
19 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm-offsets.h>
26 *************************************************************************
28 * Startup Code (reset vector)
30 * do important init only if we don't start from memory!
31 * setup Memory and board specific bits prior to relocation.
32 * relocate armboot to ram
35 *************************************************************************
42 * set the cpu to SVC32 mode
49 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
53 #ifdef CONFIG_CPU_PXA25X
54 bl lock_cache_for_stack
59 /*------------------------------------------------------------------------------*/
61 .globl c_runtime_cpu_setup
64 #ifdef CONFIG_CPU_PXA25X
66 * Unlock (actually, disable) the cache now that board_init_f
67 * is done. We could do this earlier but we would need to add
68 * a new C runtime hook, whereas c_runtime_cpu_setup already
70 * As this routine is just a call to cpu_init_crit, let us
71 * tail-optimize and do a simple branch here.
79 *************************************************************************
81 * CPU_init_critical registers
83 * setup important registers
86 *************************************************************************
88 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
94 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
95 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
98 * disable MMU stuff and caches
100 mrc p15, 0, r0, c1, c0, 0
101 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
102 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
103 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
104 mcr p15, 0, r0, c1, c0, 0
106 mov pc, lr /* back to my caller */
107 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
110 * Enable MMU to use DCache as DRAM.
112 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
113 * other possible memory available to hold stack.
115 #ifdef CONFIG_CPU_PXA25X
117 mrc p15, 0, \reg, c2, c0, 0
121 lock_cache_for_stack:
122 /* Domain access -- enable for all CPs */
124 mcr p15, 0, r0, c3, c0, 0
126 /* Point TTBR to MMU table */
128 mcr p15, 0, r0, c2, c0, 0
130 /* Kick in MMU, ICache, DCache, BTB */
131 mrc p15, 0, r0, c1, c0, 0
136 mcr p15, 0, r0, c1, c0, 0
139 /* Unlock Icache, Dcache */
140 mcr p15, 0, r0, c9, c1, 1
141 mcr p15, 0, r0, c9, c2, 1
143 /* Flush Icache, Dcache, BTB */
144 mcr p15, 0, r0, c7, c7, 0
146 /* Unlock I-TLB, D-TLB */
147 mcr p15, 0, r0, c10, c4, 1
148 mcr p15, 0, r0, c10, c8, 1
151 mcr p15, 0, r0, c8, c7, 0
153 /* Allocate 4096 bytes of Dcache as RAM */
155 /* Drain pending loads and stores */
156 mcr p15, 0, r0, c7, c10, 4
161 mcr p15, 0, r0, c9, c2, 0
164 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
169 mcr p15, 0, r1, c7, c2, 5
170 /* Drain pending loads and stores */
171 mcr p15, 0, r0, c7, c10, 4
178 /* Drain pending loads and stores */
179 mcr p15, 0, r0, c7, c10, 4
181 mcr p15, 0, r2, c9, c2, 0
186 .section .mmutable, "a"
189 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
192 .word (__base << 20) | 0xc12
193 .set __base, __base + 1
196 /* 0xfff00000 : 1:1, cached mapping */
197 .word (0xfff << 20) | 0x1c1e
198 #endif /* CONFIG_CPU_PXA25X */