2 * armboot - Startup Code for XScale CPU-core
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
19 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm-offsets.h>
26 #ifdef CONFIG_CPU_PXA25X
27 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
28 #error "Init SP address must be set to 0xfffff800 for PXA250"
34 #ifdef CONFIG_SPL_BUILD
51 .word 0x12345678 /* now 16*4=64 */
53 ldr pc, _undefined_instruction
54 ldr pc, _software_interrupt
55 ldr pc, _prefetch_abort
61 _undefined_instruction: .word undefined_instruction
62 _software_interrupt: .word software_interrupt
63 _prefetch_abort: .word prefetch_abort
64 _data_abort: .word data_abort
65 _not_used: .word not_used
68 _pad: .word 0x12345678 /* now 16*4=64 */
69 #endif /* CONFIG_SPL_BUILD */
73 .balignl 16,0xdeadbeef
75 *************************************************************************
77 * Startup Code (reset vector)
79 * do important init only if we don't start from memory!
80 * setup Memory and board specific bits prior to relocation.
81 * relocate armboot to ram
84 *************************************************************************
89 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
90 .word CONFIG_SPL_TEXT_BASE
92 .word CONFIG_SYS_TEXT_BASE
96 * These are defined in the board-specific linker script.
97 * Subtracting _start from them lets the linker put their
98 * relative position in the executable instead of leaving
101 .globl _bss_start_ofs
103 .word __bss_start - _start
107 .word __bss_end - _start
113 #ifdef CONFIG_USE_IRQ
114 /* IRQ stack memory (calculated at run-time) */
115 .globl IRQ_STACK_START
119 /* IRQ stack memory (calculated at run-time) */
120 .globl FIQ_STACK_START
125 /* IRQ stack memory (calculated at run-time) + 8 bytes */
126 .globl IRQ_STACK_START_IN
131 * the actual reset code
136 * set the cpu to SVC32 mode
143 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
147 #ifdef CONFIG_CPU_PXA25X
148 bl lock_cache_for_stack
153 /*------------------------------------------------------------------------------*/
155 .globl c_runtime_cpu_setup
158 #ifdef CONFIG_CPU_PXA25X
160 * Unlock (actually, disable) the cache now that board_init_f
161 * is done. We could do this earlier but we would need to add
162 * a new C runtime hook, whereas c_runtime_cpu_setup already
164 * As this routine is just a call to cpu_init_crit, let us
165 * tail-optimize and do a simple branch here.
173 *************************************************************************
175 * CPU_init_critical registers
177 * setup important registers
178 * setup memory timing
180 *************************************************************************
182 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
185 * flush v4 I/D caches
188 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
189 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
192 * disable MMU stuff and caches
194 mrc p15, 0, r0, c1, c0, 0
195 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
196 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
197 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
198 mcr p15, 0, r0, c1, c0, 0
200 mov pc, lr /* back to my caller */
201 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
203 #ifndef CONFIG_SPL_BUILD
205 *************************************************************************
209 *************************************************************************
214 #define S_FRAME_SIZE 72
236 #define MODE_SVC 0x13
240 * use bad_save_user_regs for abort/prefetch/undef/swi ...
241 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
244 .macro bad_save_user_regs
245 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
246 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
248 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
249 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
250 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
254 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
255 mov r0, sp @ save current stack into r0 (param register)
258 .macro irq_save_user_regs
259 sub sp, sp, #S_FRAME_SIZE
260 stmia sp, {r0 - r12} @ Calling r0-r12
261 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
262 stmdb r8, {sp, lr}^ @ Calling SP, LR
263 str lr, [r8, #0] @ Save calling PC
265 str r6, [r8, #4] @ Save CPSR
266 str r0, [r8, #8] @ Save OLD_R0
270 .macro irq_restore_user_regs
271 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
273 ldr lr, [sp, #S_PC] @ Get PC
274 add sp, sp, #S_FRAME_SIZE
275 subs pc, lr, #4 @ return & move spsr_svc into cpsr
279 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
281 str lr, [r13] @ save caller lr in position 0 of saved stack
282 mrs lr, spsr @ get the spsr
283 str lr, [r13, #4] @ save spsr in position 1 of saved stack
285 mov r13, #MODE_SVC @ prepare SVC-Mode
287 msr spsr, r13 @ switch modes, make sure moves will execute
288 mov lr, pc @ capture return pc
289 movs pc, lr @ jump to next instruction & switch modes.
292 .macro get_bad_stack_swi
293 sub r13, r13, #4 @ space on current stack for scratch reg.
294 str r0, [r13] @ save R0's value.
295 ldr r0, IRQ_STACK_START_IN @ get data regions start
296 str lr, [r0] @ save caller lr in position 0 of saved stack
297 mrs lr, spsr @ get the spsr
298 str lr, [r0, #4] @ save spsr in position 1 of saved stack
299 ldr lr, [r0] @ restore lr
300 ldr r0, [r13] @ restore r0
301 add r13, r13, #4 @ pop stack entry
304 .macro get_irq_stack @ setup IRQ stack
305 ldr sp, IRQ_STACK_START
308 .macro get_fiq_stack @ setup FIQ stack
309 ldr sp, FIQ_STACK_START
311 #endif /* CONFIG_SPL_BUILD */
316 #ifdef CONFIG_SPL_BUILD
319 ldr sp, _TEXT_BASE /* use 32 words about stack */
320 bl hang /* hang and never return */
321 #else /* !CONFIG_SPL_BUILD */
323 undefined_instruction:
326 bl do_undefined_instruction
332 bl do_software_interrupt
352 #ifdef CONFIG_USE_IRQ
359 irq_restore_user_regs
364 /* someone ought to write a more effiction fiq_save_user_regs */
367 irq_restore_user_regs
385 #endif /* CONFIG_SPL_BUILD */
389 * Enable MMU to use DCache as DRAM.
391 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
392 * other possible memory available to hold stack.
394 #ifdef CONFIG_CPU_PXA25X
396 mrc p15, 0, \reg, c2, c0, 0
400 lock_cache_for_stack:
401 /* Domain access -- enable for all CPs */
403 mcr p15, 0, r0, c3, c0, 0
405 /* Point TTBR to MMU table */
407 mcr p15, 0, r0, c2, c0, 0
409 /* Kick in MMU, ICache, DCache, BTB */
410 mrc p15, 0, r0, c1, c0, 0
415 mcr p15, 0, r0, c1, c0, 0
418 /* Unlock Icache, Dcache */
419 mcr p15, 0, r0, c9, c1, 1
420 mcr p15, 0, r0, c9, c2, 1
422 /* Flush Icache, Dcache, BTB */
423 mcr p15, 0, r0, c7, c7, 0
425 /* Unlock I-TLB, D-TLB */
426 mcr p15, 0, r0, c10, c4, 1
427 mcr p15, 0, r0, c10, c8, 1
430 mcr p15, 0, r0, c8, c7, 0
432 /* Allocate 4096 bytes of Dcache as RAM */
434 /* Drain pending loads and stores */
435 mcr p15, 0, r0, c7, c10, 4
440 mcr p15, 0, r0, c9, c2, 0
443 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
448 mcr p15, 0, r1, c7, c2, 5
449 /* Drain pending loads and stores */
450 mcr p15, 0, r0, c7, c10, 4
457 /* Drain pending loads and stores */
458 mcr p15, 0, r0, c7, c10, 4
460 mcr p15, 0, r2, c9, c2, 0
465 .section .mmutable, "a"
468 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
471 .word (__base << 20) | 0xc12
472 .set __base, __base + 1
475 /* 0xfff00000 : 1:1, cached mapping */
476 .word (0xfff << 20) | 0x1c1e
477 #endif /* CONFIG_CPU_PXA25X */