2 * armboot - Startup Code for XScale CPU-core
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm-offsets.h>
42 #ifdef CONFIG_CPU_PXA25X
43 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
44 #error "Init SP address must be set to 0xfffff800 for PXA250"
50 #ifdef CONFIG_SPL_BUILD
67 .word 0x12345678 /* now 16*4=64 */
69 ldr pc, _undefined_instruction
70 ldr pc, _software_interrupt
71 ldr pc, _prefetch_abort
77 _undefined_instruction: .word undefined_instruction
78 _software_interrupt: .word software_interrupt
79 _prefetch_abort: .word prefetch_abort
80 _data_abort: .word data_abort
81 _not_used: .word not_used
84 _pad: .word 0x12345678 /* now 16*4=64 */
85 #endif /* CONFIG_SPL_BUILD */
89 .balignl 16,0xdeadbeef
91 *************************************************************************
93 * Startup Code (reset vector)
95 * do important init only if we don't start from memory!
96 * setup Memory and board specific bits prior to relocation.
97 * relocate armboot to ram
100 *************************************************************************
105 #ifdef CONFIG_SPL_BUILD
106 .word CONFIG_SPL_TEXT_BASE
108 .word CONFIG_SYS_TEXT_BASE
112 * These are defined in the board-specific linker script.
113 * Subtracting _start from them lets the linker put their
114 * relative position in the executable instead of leaving
117 .globl _bss_start_ofs
119 .word __bss_start - _start
123 .word __bss_end__ - _start
129 #ifdef CONFIG_USE_IRQ
130 /* IRQ stack memory (calculated at run-time) */
131 .globl IRQ_STACK_START
135 /* IRQ stack memory (calculated at run-time) */
136 .globl FIQ_STACK_START
141 /* IRQ stack memory (calculated at run-time) + 8 bytes */
142 .globl IRQ_STACK_START_IN
147 * the actual reset code
152 * set the cpu to SVC32 mode
159 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
163 #ifdef CONFIG_CPU_PXA25X
164 bl lock_cache_for_stack
167 /* Set stackpointer in internal RAM to call board_init_f */
169 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
170 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
174 /*------------------------------------------------------------------------------*/
175 #ifndef CONFIG_SPL_BUILD
177 * void relocate_code (addr_sp, gd, addr_moni)
179 * This "function" does not return, instead it continues in RAM
180 * after relocating the monitor code.
185 mov r4, r0 /* save addr_sp */
186 mov r5, r1 /* save addr of gd */
187 mov r6, r2 /* save addr of destination */
189 /* Set up the stack */
193 /* Disable the Dcache RAM lock for stack now */
194 #ifdef CONFIG_CPU_PXA25X
200 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
201 beq clear_bss /* skip relocation */
202 mov r1, r6 /* r1 <- scratch for copy_loop */
203 ldr r3, _bss_start_ofs
204 add r2, r0, r3 /* r2 <- source end address */
207 ldmia r0!, {r9-r10} /* copy from source address [r0] */
208 stmia r1!, {r9-r10} /* copy to target address [r1] */
209 cmp r0, r2 /* until source end address [r2] */
212 #ifndef CONFIG_SPL_BUILD
214 * fix .rel.dyn relocations
216 ldr r0, _TEXT_BASE /* r0 <- Text base */
217 sub r9, r6, r0 /* r9 <- relocation offset */
218 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
219 add r10, r10, r0 /* r10 <- sym table in FLASH */
220 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
221 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
222 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
223 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
225 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
226 add r0, r0, r9 /* r0 <- location to fix up in RAM */
229 cmp r7, #23 /* relative fixup? */
231 cmp r7, #2 /* absolute fixup? */
233 /* ignore unknown type of fixup */
236 /* absolute fix: set location to (offset) symbol value */
237 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
238 add r1, r10, r1 /* r1 <- address of symbol in table */
239 ldr r1, [r1, #4] /* r1 <- symbol value */
240 add r1, r1, r9 /* r1 <- relocated sym addr */
243 /* relative fix: increase location by offset */
248 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
254 #ifndef CONFIG_SPL_BUILD
255 ldr r0, _bss_start_ofs
257 mov r4, r6 /* reloc addr */
260 mov r2, #0x00000000 /* clear */
262 clbss_l:cmp r0, r1 /* clear loop... */
263 bhs clbss_e /* if reached end of bss, exit */
268 #endif /* #ifndef CONFIG_SPL_BUILD */
271 * We are done. Do not return, instead branch to second part of board
272 * initialization, now running from RAM.
274 #ifdef CONFIG_ONENAND_SPL
275 ldr r0, _onenand_boot_ofs
282 ldr r0, _board_init_r_ofs
286 /* setup parameters for board_init_r */
287 mov r0, r5 /* gd_t */
288 mov r1, r6 /* dest_addr */
293 .word board_init_r - _start
297 .word __rel_dyn_start - _start
299 .word __rel_dyn_end - _start
301 .word __dynsym_start - _start
304 *************************************************************************
306 * CPU_init_critical registers
308 * setup important registers
309 * setup memory timing
311 *************************************************************************
313 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
316 * flush v4 I/D caches
319 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
320 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
323 * disable MMU stuff and caches
325 mrc p15, 0, r0, c1, c0, 0
326 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
327 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
328 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
329 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
330 mcr p15, 0, r0, c1, c0, 0
332 mov pc, lr /* back to my caller */
333 #endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
335 #ifndef CONFIG_SPL_BUILD
337 *************************************************************************
341 *************************************************************************
346 #define S_FRAME_SIZE 72
368 #define MODE_SVC 0x13
372 * use bad_save_user_regs for abort/prefetch/undef/swi ...
373 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
376 .macro bad_save_user_regs
377 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
378 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
380 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
381 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
382 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
386 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
387 mov r0, sp @ save current stack into r0 (param register)
390 .macro irq_save_user_regs
391 sub sp, sp, #S_FRAME_SIZE
392 stmia sp, {r0 - r12} @ Calling r0-r12
393 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
394 stmdb r8, {sp, lr}^ @ Calling SP, LR
395 str lr, [r8, #0] @ Save calling PC
397 str r6, [r8, #4] @ Save CPSR
398 str r0, [r8, #8] @ Save OLD_R0
402 .macro irq_restore_user_regs
403 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
405 ldr lr, [sp, #S_PC] @ Get PC
406 add sp, sp, #S_FRAME_SIZE
407 subs pc, lr, #4 @ return & move spsr_svc into cpsr
411 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
413 str lr, [r13] @ save caller lr in position 0 of saved stack
414 mrs lr, spsr @ get the spsr
415 str lr, [r13, #4] @ save spsr in position 1 of saved stack
417 mov r13, #MODE_SVC @ prepare SVC-Mode
419 msr spsr, r13 @ switch modes, make sure moves will execute
420 mov lr, pc @ capture return pc
421 movs pc, lr @ jump to next instruction & switch modes.
424 .macro get_bad_stack_swi
425 sub r13, r13, #4 @ space on current stack for scratch reg.
426 str r0, [r13] @ save R0's value.
427 ldr r0, IRQ_STACK_START_IN @ get data regions start
428 str lr, [r0] @ save caller lr in position 0 of saved stack
429 mrs r0, spsr @ get the spsr
430 str lr, [r0, #4] @ save spsr in position 1 of saved stack
431 ldr r0, [r13] @ restore r0
432 add r13, r13, #4 @ pop stack entry
435 .macro get_irq_stack @ setup IRQ stack
436 ldr sp, IRQ_STACK_START
439 .macro get_fiq_stack @ setup FIQ stack
440 ldr sp, FIQ_STACK_START
442 #endif /* CONFIG_SPL_BUILD */
447 #ifdef CONFIG_SPL_BUILD
450 ldr sp, _TEXT_BASE /* use 32 words about stack */
451 bl hang /* hang and never return */
452 #else /* !CONFIG_SPL_BUILD */
454 undefined_instruction:
457 bl do_undefined_instruction
463 bl do_software_interrupt
483 #ifdef CONFIG_USE_IRQ
490 irq_restore_user_regs
495 /* someone ought to write a more effiction fiq_save_user_regs */
498 irq_restore_user_regs
516 #endif /* CONFIG_SPL_BUILD */
520 * Enable MMU to use DCache as DRAM.
522 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
523 * other possible memory available to hold stack.
525 #ifdef CONFIG_CPU_PXA25X
527 mrc p15, 0, \reg, c2, c0, 0
531 lock_cache_for_stack:
532 /* Domain access -- enable for all CPs */
534 mcr p15, 0, r0, c3, c0, 0
536 /* Point TTBR to MMU table */
538 mcr p15, 0, r0, c2, c0, 0
540 /* Kick in MMU, ICache, DCache, BTB */
541 mrc p15, 0, r0, c1, c0, 0
546 mcr p15, 0, r0, c1, c0, 0
549 /* Unlock Icache, Dcache */
550 mcr p15, 0, r0, c9, c1, 1
551 mcr p15, 0, r0, c9, c2, 1
553 /* Flush Icache, Dcache, BTB */
554 mcr p15, 0, r0, c7, c7, 0
556 /* Unlock I-TLB, D-TLB */
557 mcr p15, 0, r0, c10, c4, 1
558 mcr p15, 0, r0, c10, c8, 1
561 mcr p15, 0, r0, c8, c7, 0
563 /* Allocate 4096 bytes of Dcache as RAM */
565 /* Drain pending loads and stores */
566 mcr p15, 0, r0, c7, c10, 4
571 mcr p15, 0, r0, c9, c2, 0
574 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
579 mcr p15, 0, r1, c7, c2, 5
580 /* Drain pending loads and stores */
581 mcr p15, 0, r0, c7, c10, 4
588 /* Drain pending loads and stores */
589 mcr p15, 0, r0, c7, c10, 4
591 mcr p15, 0, r2, c9, c2, 0
596 .section .mmutable, "a"
599 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */
602 .word (__base << 20) | 0xc12
603 .set __base, __base + 1
606 /* 0xfff00000 : 1:1, cached mapping */
607 .word (0xfff << 20) | 0x1c1e
608 #endif /* CONFIG_CPU_PXA25X */