2 * armboot - Startup Code for XScale
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
9 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
11 * Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
35 #include <asm/arch/pxa-regs.h>
37 /* takes care the CP15 update has taken place */
39 mrc p15,0,\reg,c2,c0,0
46 #ifdef CONFIG_PRELOADER
63 .word 0x12345678 /* now 16*4=64 */
65 ldr pc, _undefined_instruction
66 ldr pc, _software_interrupt
67 ldr pc, _prefetch_abort
73 _undefined_instruction: .word undefined_instruction
74 _software_interrupt: .word software_interrupt
75 _prefetch_abort: .word prefetch_abort
76 _data_abort: .word data_abort
77 _not_used: .word not_used
80 #endif /* CONFIG_PRELOADER */
82 .balignl 16,0xdeadbeef
86 * Startup Code (reset vector)
88 * do important init only if we don't start from RAM!
89 * - relocate armboot to RAM
91 * - jump to second stage
96 .word CONFIG_SYS_TEXT_BASE
99 * These are defined in the board-specific linker script.
101 .globl _bss_start_ofs
103 .word __bss_start - _start
107 .word __bss_end__ - _start
113 #ifdef CONFIG_USE_IRQ
114 /* IRQ stack memory (calculated at run-time) */
115 .globl IRQ_STACK_START
119 /* IRQ stack memory (calculated at run-time) */
120 .globl FIQ_STACK_START
123 #endif /* CONFIG_USE_IRQ */
125 #ifndef CONFIG_PRELOADER
126 /* IRQ stack memory (calculated at run-time) + 8 bytes */
127 .globl IRQ_STACK_START_IN
132 * the actual reset code
137 * set the cpu to SVC32 mode
145 * Enable MMU to use DCache as DRAM
147 /* Domain access -- enable for all CPs */
149 mcr p15, 0, r0, c3, c0, 0
151 /* Point TTBR to MMU table */
155 mcr p15, 0, r0, c2, c0, 0
157 /* !!! Hereby, check if the code is running from SRAM !!! */
158 /* If the code is running from SRAM, alias SRAM to 0x0 to simulate NOR. The code
159 * is linked to 0x0 too, so this makes things easier. */
166 /* Kick in MMU, ICache, DCache, BTB */
167 mrc p15, 0, r0, c1, c0, 0
172 mcr p15, 0, r0, c1, c0, 0
175 /* Unlock Icache, Dcache */
176 mcr p15, 0, r0, c9, c1, 1
177 mcr p15, 0, r0, c9, c2, 1
179 /* Flush Icache, Dcache, BTB */
180 mcr p15, 0, r0, c7, c7, 0
182 /* Unlock I-TLB, D-TLB */
183 mcr p15, 0, r0, c10, c4, 1
184 mcr p15, 0, r0, c10, c8, 1
187 mcr p15, 0, r0, c8, c7, 0
188 /* Allocate 4096 bytes of Dcache as RAM */
190 /* Drain pending loads and stores */
191 mcr p15, 0, r0, c7, c10, 4
196 mcr p15, 0, r0, c9, c2, 0
199 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
203 mcr p15, 0, r1, c7, c2, 5
204 /* Drain pending loads and stores */
205 mcr p15, 0, r0, c7, c10, 4
212 /* Drain pending loads and stores */
213 mcr p15, 0, r0, c7, c10, 4
215 mcr p15, 0, r2, c9, c2, 0
218 /* Jump to 0x0 ( + offset) if running from SRAM */
224 /* Set stackpointer in internal RAM to call board_init_f */
226 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
227 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
231 /*------------------------------------------------------------------------------*/
234 * void relocate_code (addr_sp, gd, addr_moni)
236 * This "function" does not return, instead it continues in RAM
237 * after relocating the monitor code.
242 mov r4, r0 /* save addr_sp */
243 mov r5, r1 /* save addr of gd */
244 mov r6, r2 /* save addr of destination */
246 /* Set up the stack */
252 beq clear_bss /* skip relocation */
253 mov r1, r6 /* r1 <- scratch for copy_loop */
254 ldr r3, _bss_start_ofs
255 add r2, r0, r3 /* r2 <- source end address */
259 ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
260 stmia r1!, {r3-r5, r7-r11} /* copy to target address [r1] */
261 cmp r0, r2 /* until source end address [r2] */
265 #ifndef CONFIG_PRELOADER
267 * fix .rel.dyn relocations
269 ldr r0, _TEXT_BASE /* r0 <- Text base */
270 sub r9, r6, r0 /* r9 <- relocation offset */
271 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
272 add r10, r10, r0 /* r10 <- sym table in FLASH */
273 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
274 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
275 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
276 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
278 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
279 add r0, r9 /* r0 <- location to fix up in RAM */
282 cmp r7, #23 /* relative fixup? */
284 cmp r7, #2 /* absolute fixup? */
286 /* ignore unknown type of fixup */
289 /* absolute fix: set location to (offset) symbol value */
290 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
291 add r1, r10, r1 /* r1 <- address of symbol in table */
292 ldr r1, [r1, #4] /* r1 <- symbol value */
293 add r1, r1, r9 /* r1 <- relocated sym addr */
296 /* relative fix: increase location by offset */
301 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
304 #endif /* #ifndef CONFIG_PRELOADER */
307 #ifndef CONFIG_PRELOADER
308 ldr r0, _bss_start_ofs
310 mov r4, r6 /* reloc addr */
313 mov r2, #0x00000000 /* clear */
315 clbss_l:str r2, [r0] /* clear loop... */
319 #endif /* #ifndef CONFIG_PRELOADER */
322 * We are done. Do not return, instead branch to second part of board
323 * initialization, now running from RAM.
325 #ifdef CONFIG_ONENAND_IPL
326 ldr r0, _start_oneboot_ofs
330 : .word start_oneboot
332 ldr r0, _board_init_r_ofs
336 /* setup parameters for board_init_r */
337 mov r0, r5 /* gd_t */
338 mov r1, r6 /* dest_addr */
343 .word board_init_r - _start
344 #endif /* CONFIG_ONENAND_IPL */
347 .word __rel_dyn_start - _start
349 .word __rel_dyn_end - _start
351 .word __dynsym_start - _start
353 #else /* CONFIG_PRELOADER */
355 /****************************************************************************/
357 /* the actual reset code for OneNAND IPL */
359 /****************************************************************************/
361 #ifndef CONFIG_PXA27X
362 #error OneNAND IPL is not supported on PXA25x and 26x due to lack of SRAM
366 /* Set CPU to SVC32 mode */
372 /* Point stack at the end of SRAM and leave 32 words for abort-stack */
375 /* Start OneNAND IPL */
376 ldr pc, =start_oneboot
378 #endif /* CONFIG_PRELOADER */
380 #ifndef CONFIG_PRELOADER
381 /****************************************************************************/
383 /* Interrupt handling */
385 /****************************************************************************/
387 /* IRQ stack frame */
389 #define S_FRAME_SIZE 72
411 #define MODE_SVC 0x13
413 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
415 .macro bad_save_user_regs
416 sub sp, sp, #S_FRAME_SIZE
417 stmia sp, {r0 - r12} /* Calling r0-r12 */
420 ldr r2, IRQ_STACK_START_IN
421 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
422 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
426 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
431 /* use irq_save_user_regs / irq_restore_user_regs for */
432 /* IRQ/FIQ handling */
434 .macro irq_save_user_regs
435 sub sp, sp, #S_FRAME_SIZE
436 stmia sp, {r0 - r12} /* Calling r0-r12 */
438 stmdb r8, {sp, lr}^ /* Calling SP, LR */
439 str lr, [r8, #0] /* Save calling PC */
441 str r6, [r8, #4] /* Save CPSR */
442 str r0, [r8, #8] /* Save OLD_R0 */
446 .macro irq_restore_user_regs
447 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
449 ldr lr, [sp, #S_PC] @ Get PC
450 add sp, sp, #S_FRAME_SIZE
451 subs pc, lr, #4 @ return & move spsr_svc into cpsr
455 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
457 str lr, [r13] @ save caller lr / spsr
461 mov r13, #MODE_SVC @ prepare SVC-Mode
467 .macro get_irq_stack @ setup IRQ stack
468 ldr sp, IRQ_STACK_START
471 .macro get_fiq_stack @ setup FIQ stack
472 ldr sp, FIQ_STACK_START
474 #endif /* CONFIG_PRELOADER
477 /****************************************************************************/
479 /* exception handlers */
481 /****************************************************************************/
483 #ifdef CONFIG_PRELOADER
486 ldr sp, _TEXT_BASE /* use 32 words abort stack */
487 bl hang /* hang and never return */
490 undefined_instruction:
493 bl do_undefined_instruction
499 bl do_software_interrupt
519 #ifdef CONFIG_USE_IRQ
526 irq_restore_user_regs
531 irq_save_user_regs /* someone ought to write a more */
532 bl do_fiq /* effiction fiq_save_user_regs */
533 irq_restore_user_regs
535 #else /* !CONFIG_USE_IRQ */
548 #endif /* CONFIG_PRELOADER */
549 #endif /* CONFIG_USE_IRQ */
551 /****************************************************************************/
553 /* Reset function: the PXA250 doesn't have a reset function, so we have to */
554 /* perform a watchdog timeout for a soft reset. */
556 /****************************************************************************/
557 /* Operating System Timer */
561 /* FIXME: this code is PXA250 specific. How is this handled on */
562 /* other XScale processors? */
566 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
570 orr r1, r1, #0x0001 /* bit0: WME */
573 /* OS timer does only wrap every 1165 seconds, so we have to set */
574 /* the match register as well. */
577 ldr r1, [r0] /* read OS timer */
578 add r1, r1, #0x800 /* let OSMR3 match after */
579 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
587 #ifndef CONFIG_PRELOADER
588 .section .mmudata, "a"
592 /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
595 .word (__base << 20) | 0xc12
596 .set __base, __base + 1
599 /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
600 .word (0xa00 << 20) | 0x1c1e
604 .word (__base << 20) | 0xc12
605 .set __base, __base + 1
607 #endif /* CONFIG_PRELOADER */