2 * armboot - Startup Code for XScale CPU-core
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
13 * Copyright (C) 2003 Kshitij <kshitij@ti.com>
14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 #include <asm-offsets.h>
43 #ifdef CONFIG_SPL_BUILD
60 .word 0x12345678 /* now 16*4=64 */
62 ldr pc, _undefined_instruction
63 ldr pc, _software_interrupt
64 ldr pc, _prefetch_abort
70 _undefined_instruction: .word undefined_instruction
71 _software_interrupt: .word software_interrupt
72 _prefetch_abort: .word prefetch_abort
73 _data_abort: .word data_abort
74 _not_used: .word not_used
77 _pad: .word 0x12345678 /* now 16*4=64 */
78 #endif /* CONFIG_SPL_BUILD */
82 .balignl 16,0xdeadbeef
84 *************************************************************************
86 * Startup Code (reset vector)
88 * do important init only if we don't start from memory!
89 * setup Memory and board specific bits prior to relocation.
90 * relocate armboot to ram
93 *************************************************************************
98 #ifdef CONFIG_SPL_BUILD
99 .word CONFIG_SPL_TEXT_BASE
101 .word CONFIG_SYS_TEXT_BASE
105 * These are defined in the board-specific linker script.
106 * Subtracting _start from them lets the linker put their
107 * relative position in the executable instead of leaving
110 .globl _bss_start_ofs
112 .word __bss_start - _start
116 .word __bss_end__ - _start
122 #ifdef CONFIG_USE_IRQ
123 /* IRQ stack memory (calculated at run-time) */
124 .globl IRQ_STACK_START
128 /* IRQ stack memory (calculated at run-time) */
129 .globl FIQ_STACK_START
134 /* IRQ stack memory (calculated at run-time) + 8 bytes */
135 .globl IRQ_STACK_START_IN
140 * the actual reset code
145 * set the cpu to SVC32 mode
152 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
156 /* Set stackpointer in internal RAM to call board_init_f */
158 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
159 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
163 /*------------------------------------------------------------------------------*/
164 #ifndef CONFIG_SPL_BUILD
166 * void relocate_code (addr_sp, gd, addr_moni)
168 * This "function" does not return, instead it continues in RAM
169 * after relocating the monitor code.
174 mov r4, r0 /* save addr_sp */
175 mov r5, r1 /* save addr of gd */
176 mov r6, r2 /* save addr of destination */
178 /* Set up the stack */
184 beq clear_bss /* skip relocation */
185 mov r1, r6 /* r1 <- scratch for copy_loop */
186 ldr r3, _bss_start_ofs
187 add r2, r0, r3 /* r2 <- source end address */
190 ldmia r0!, {r9-r10} /* copy from source address [r0] */
191 stmia r1!, {r9-r10} /* copy to target address [r1] */
192 cmp r0, r2 /* until source end address [r2] */
195 #ifndef CONFIG_SPL_BUILD
197 * fix .rel.dyn relocations
199 ldr r0, _TEXT_BASE /* r0 <- Text base */
200 sub r9, r6, r0 /* r9 <- relocation offset */
201 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
202 add r10, r10, r0 /* r10 <- sym table in FLASH */
203 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
204 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
205 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
206 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
208 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
209 add r0, r0, r9 /* r0 <- location to fix up in RAM */
212 cmp r7, #23 /* relative fixup? */
214 cmp r7, #2 /* absolute fixup? */
216 /* ignore unknown type of fixup */
219 /* absolute fix: set location to (offset) symbol value */
220 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
221 add r1, r10, r1 /* r1 <- address of symbol in table */
222 ldr r1, [r1, #4] /* r1 <- symbol value */
223 add r1, r1, r9 /* r1 <- relocated sym addr */
226 /* relative fix: increase location by offset */
231 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
237 #ifndef CONFIG_SPL_BUILD
238 ldr r0, _bss_start_ofs
240 mov r4, r6 /* reloc addr */
243 mov r2, #0x00000000 /* clear */
245 clbss_l:str r2, [r0] /* clear loop... */
249 #endif /* #ifndef CONFIG_SPL_BUILD */
252 * We are done. Do not return, instead branch to second part of board
253 * initialization, now running from RAM.
255 #ifdef CONFIG_ONENAND_SPL
256 ldr r0, _onenand_boot_ofs
263 ldr r0, _board_init_r_ofs
267 /* setup parameters for board_init_r */
268 mov r0, r5 /* gd_t */
269 mov r1, r6 /* dest_addr */
274 .word board_init_r - _start
278 .word __rel_dyn_start - _start
280 .word __rel_dyn_end - _start
282 .word __dynsym_start - _start
285 *************************************************************************
287 * CPU_init_critical registers
289 * setup important registers
290 * setup memory timing
292 *************************************************************************
294 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
297 * flush v4 I/D caches
300 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
301 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
304 * disable MMU stuff and caches
306 mrc p15, 0, r0, c1, c0, 0
307 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
308 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
309 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
310 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
311 mcr p15, 0, r0, c1, c0, 0
313 mov pc, lr /* back to my caller */
314 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
316 #ifndef CONFIG_SPL_BUILD
318 *************************************************************************
322 *************************************************************************
327 #define S_FRAME_SIZE 72
349 #define MODE_SVC 0x13
353 * use bad_save_user_regs for abort/prefetch/undef/swi ...
354 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
357 .macro bad_save_user_regs
358 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
359 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
361 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
362 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
363 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
367 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
368 mov r0, sp @ save current stack into r0 (param register)
371 .macro irq_save_user_regs
372 sub sp, sp, #S_FRAME_SIZE
373 stmia sp, {r0 - r12} @ Calling r0-r12
374 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
375 stmdb r8, {sp, lr}^ @ Calling SP, LR
376 str lr, [r8, #0] @ Save calling PC
378 str r6, [r8, #4] @ Save CPSR
379 str r0, [r8, #8] @ Save OLD_R0
383 .macro irq_restore_user_regs
384 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
386 ldr lr, [sp, #S_PC] @ Get PC
387 add sp, sp, #S_FRAME_SIZE
388 subs pc, lr, #4 @ return & move spsr_svc into cpsr
392 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
394 str lr, [r13] @ save caller lr in position 0 of saved stack
395 mrs lr, spsr @ get the spsr
396 str lr, [r13, #4] @ save spsr in position 1 of saved stack
398 mov r13, #MODE_SVC @ prepare SVC-Mode
400 msr spsr, r13 @ switch modes, make sure moves will execute
401 mov lr, pc @ capture return pc
402 movs pc, lr @ jump to next instruction & switch modes.
405 .macro get_bad_stack_swi
406 sub r13, r13, #4 @ space on current stack for scratch reg.
407 str r0, [r13] @ save R0's value.
408 ldr r0, IRQ_STACK_START_IN @ get data regions start
409 str lr, [r0] @ save caller lr in position 0 of saved stack
410 mrs r0, spsr @ get the spsr
411 str lr, [r0, #4] @ save spsr in position 1 of saved stack
412 ldr r0, [r13] @ restore r0
413 add r13, r13, #4 @ pop stack entry
416 .macro get_irq_stack @ setup IRQ stack
417 ldr sp, IRQ_STACK_START
420 .macro get_fiq_stack @ setup FIQ stack
421 ldr sp, FIQ_STACK_START
423 #endif /* CONFIG_SPL_BUILD */
428 #ifdef CONFIG_SPL_BUILD
431 ldr sp, _TEXT_BASE /* use 32 words about stack */
432 bl hang /* hang and never return */
433 #else /* !CONFIG_SPL_BUILD */
435 undefined_instruction:
438 bl do_undefined_instruction
444 bl do_software_interrupt
464 #ifdef CONFIG_USE_IRQ
471 irq_restore_user_regs
476 /* someone ought to write a more effiction fiq_save_user_regs */
479 irq_restore_user_regs
497 #endif /* CONFIG_SPL_BUILD */