2 * Startup Code for S3C44B0 CPU-core
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42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
48 add pc, pc, #0x0c000000
50 .balignl 16,0xdeadbeef
54 *************************************************************************
56 * Startup Code (reset vector)
58 * do important init only if we don't start from memory!
59 * relocate u-boot to ram
61 * jump to second stage
63 *************************************************************************
68 .word CONFIG_SYS_TEXT_BASE
70 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
77 * These are defined in the board-specific linker script.
88 /* IRQ stack memory (calculated at run-time) */
89 .globl IRQ_STACK_START
93 /* IRQ stack memory (calculated at run-time) */
94 .globl FIQ_STACK_START
99 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
100 /* IRQ stack memory (calculated at run-time) + 8 bytes */
101 .globl IRQ_STACK_START_IN
105 .globl _datarel_start
107 .word __datarel_start
109 .globl _datarelrolocal_start
110 _datarelrolocal_start:
111 .word __datarelrolocal_start
113 .globl _datarellocal_start
115 .word __datarellocal_start
117 .globl _datarelro_start
119 .word __datarelro_start
130 * the actual reset code
135 * set the cpu to SVC32 mode
143 * we do sys-critical inits only at reboot,
144 * not when booting from ram!
146 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
149 * before relocating, we have to setup RAM timing
150 * because memory timing is board-dependend, you will
151 * find a lowlevel_init.S in your board directory.
156 /* Set stackpointer in internal RAM to call board_init_f */
158 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
162 /*------------------------------------------------------------------------------*/
165 * void relocate_code (addr_sp, gd, addr_moni)
167 * This "function" does not return, instead it continues in RAM
168 * after relocating the monitor code.
173 mov r4, r0 /* save addr_sp */
174 mov r5, r1 /* save addr of gd */
175 mov r6, r2 /* save addr of destination */
176 mov r7, r2 /* save addr of destination */
178 /* Set up the stack */
185 sub r2, r3, r2 /* r2 <- size of armboot */
186 add r2, r0, r2 /* r2 <- source end address */
190 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
192 ldmia r0!, {r9-r10} /* copy from source address [r0] */
193 stmia r6!, {r9-r10} /* copy to target address [r1] */
194 cmp r0, r2 /* until source end address [r2] */
197 #ifndef CONFIG_PRELOADER
198 /* fix got entries */
199 ldr r1, _TEXT_BASE /* Text base */
200 mov r0, r7 /* reloc addr */
201 ldr r2, _got_start /* addr in Flash */
202 ldr r3, _got_end /* addr in Flash */
218 now copy to sram the interrupt vector
229 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
232 #ifndef CONFIG_PRELOADER
235 ldr r3, _TEXT_BASE /* Text base */
236 mov r4, r7 /* reloc addr */
241 mov r2, #0x00000000 /* clear */
243 clbss_l:str r2, [r0] /* clear loop... */
253 * We are done. Do not return, instead branch to second part of board
254 * initialization, now running from RAM.
257 ldr r2, _board_init_r
259 add r2, r2, r7 /* position from board_init_r in RAM */
260 /* setup parameters for board_init_r */
261 mov r0, r5 /* gd_t */
262 mov r1, r7 /* dest_addr */
267 _board_init_r: .word board_init_r
269 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
271 * the actual reset code
276 * set the cpu to SVC32 mode
284 * we do sys-critical inits only at reboot,
285 * not when booting from ram!
288 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
291 * before relocating, we have to setup RAM timing
292 * because memory timing is board-dependend, you will
293 * find a lowlevel_init.S in your board directory.
298 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
299 relocate: /* relocate U-Boot to RAM */
300 adr r0, _start /* r0 <- current position of code */
301 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
302 cmp r0, r1 /* don't reloc during debug */
305 ldr r2, _armboot_start
307 sub r2, r3, r2 /* r2 <- size of armboot */
308 add r2, r0, r2 /* r2 <- source end address */
311 ldmia r0!, {r3-r10} /* copy from source address [r0] */
312 stmia r1!, {r3-r10} /* copy to target address [r1] */
313 cmp r0, r2 /* until source end address [r2] */
317 now copy to sram the interrupt vector
328 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
330 /* Set up the stack */
332 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
333 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
334 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
335 #ifdef CONFIG_USE_IRQ
336 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
338 sub sp, r0, #12 /* leave 3 words for abort-stack */
339 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
341 ldr pc, _start_armboot
343 _start_armboot: .word start_armboot
345 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
348 *************************************************************************
350 * CPU_init_critical registers
352 * setup important registers
353 * setup memory timing
355 *************************************************************************
358 #define INTCON (0x01c00000+0x200000)
359 #define INTMSK (0x01c00000+0x20000c)
360 #define LOCKTIME (0x01c00000+0x18000c)
361 #define PLLCON (0x01c00000+0x180000)
362 #define CLKCON (0x01c00000+0x180004)
363 #define WTCON (0x01c00000+0x130000)
365 /* disable watch dog */
371 * mask all IRQs by clearing all bits in the INTMRs
381 /* Set Clock Control Register */
388 #if CONFIG_S3C44B0_CLOCK_SPEED==66
389 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
390 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
391 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
393 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
405 /*************************************************/
406 /* interrupt vectors */
407 /*************************************************/
410 b undefined_instruction
418 /*************************************************/
420 undefined_instruction:
437 /* we *should* never reach this */