2 * Startup Code for S3C44B0 CPU-core
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14 #include <asm-offsets.h>
25 add pc, pc, #0x0c000000
26 add pc, pc, #0x0c000000
27 add pc, pc, #0x0c000000
28 add pc, pc, #0x0c000000
29 add pc, pc, #0x0c000000
30 add pc, pc, #0x0c000000
31 add pc, pc, #0x0c000000
33 .balignl 16,0xdeadbeef
37 *************************************************************************
39 * Startup Code (reset vector)
41 * do important init only if we don't start from memory!
42 * relocate u-boot to ram
44 * jump to second stage
46 *************************************************************************
51 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
52 .word CONFIG_SPL_TEXT_BASE
54 .word CONFIG_SYS_TEXT_BASE
58 * These are defined in the board-specific linker script.
59 * Subtracting _start from them lets the linker put their
60 * relative position in the executable instead of leaving
65 .word __bss_start - _start
69 .word __bss_end - _start
76 /* IRQ stack memory (calculated at run-time) */
77 .globl IRQ_STACK_START
81 /* IRQ stack memory (calculated at run-time) */
82 .globl FIQ_STACK_START
87 /* IRQ stack memory (calculated at run-time) + 8 bytes */
88 .globl IRQ_STACK_START_IN
93 * the actual reset code
98 * set the cpu to SVC32 mode
106 * we do sys-critical inits only at reboot,
107 * not when booting from ram!
109 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
112 * before relocating, we have to setup RAM timing
113 * because memory timing is board-dependend, you will
114 * find a lowlevel_init.S in your board directory.
121 /*------------------------------------------------------------------------------*/
123 .globl c_runtime_cpu_setup
129 *************************************************************************
131 * CPU_init_critical registers
133 * setup important registers
134 * setup memory timing
136 *************************************************************************
139 #define INTCON (0x01c00000+0x200000)
140 #define INTMSK (0x01c00000+0x20000c)
141 #define LOCKTIME (0x01c00000+0x18000c)
142 #define PLLCON (0x01c00000+0x180000)
143 #define CLKCON (0x01c00000+0x180004)
144 #define WTCON (0x01c00000+0x130000)
146 /* disable watch dog */
152 * mask all IRQs by clearing all bits in the INTMRs
162 /* Set Clock Control Register */
169 #if CONFIG_S3C44B0_CLOCK_SPEED==66
170 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
171 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
172 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
174 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
186 /*************************************************/
187 /* interrupt vectors */
188 /*************************************************/
191 b undefined_instruction
199 /*************************************************/
201 undefined_instruction:
218 /* we *should* never reach this */