2 * Startup Code for S3C44B0 CPU-core
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30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
68 .word CONFIG_SPL_TEXT_BASE
70 .word CONFIG_SYS_TEXT_BASE
74 * These are defined in the board-specific linker script.
75 * Subtracting _start from them lets the linker put their
76 * relative position in the executable instead of leaving
81 .word __bss_start - _start
83 .globl _image_copy_end_ofs
85 .word __image_copy_end - _start
89 .word __bss_end - _start
96 /* IRQ stack memory (calculated at run-time) */
97 .globl IRQ_STACK_START
101 /* IRQ stack memory (calculated at run-time) */
102 .globl FIQ_STACK_START
107 /* IRQ stack memory (calculated at run-time) + 8 bytes */
108 .globl IRQ_STACK_START_IN
113 * the actual reset code
118 * set the cpu to SVC32 mode
126 * we do sys-critical inits only at reboot,
127 * not when booting from ram!
129 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
132 * before relocating, we have to setup RAM timing
133 * because memory timing is board-dependend, you will
134 * find a lowlevel_init.S in your board directory.
141 /*------------------------------------------------------------------------------*/
144 * void relocate_code(addr_moni)
146 * This function relocates the monitor code.
150 mov r6, r0 /* save addr of destination */
153 subs r9, r6, r0 /* r9 <- relocation offset */
154 beq relocate_done /* skip relocation */
155 mov r1, r6 /* r1 <- scratch for copy_loop */
156 ldr r3, _image_copy_end_ofs
157 add r2, r0, r3 /* r2 <- source end address */
160 ldmia r0!, {r10-r11} /* copy from source address [r0] */
161 stmia r1!, {r10-r11} /* copy to target address [r1] */
162 cmp r0, r2 /* until source end address [r2] */
165 #ifndef CONFIG_SPL_BUILD
167 * fix .rel.dyn relocations
169 ldr r0, _TEXT_BASE /* r0 <- Text base */
170 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
171 add r10, r10, r0 /* r10 <- sym table in FLASH */
172 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
173 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
174 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
175 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
177 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
178 add r0, r0, r9 /* r0 <- location to fix up in RAM */
181 cmp r7, #23 /* relative fixup? */
183 cmp r7, #2 /* absolute fixup? */
185 /* ignore unknown type of fixup */
188 /* absolute fix: set location to (offset) symbol value */
189 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
190 add r1, r10, r1 /* r1 <- address of symbol in table */
191 ldr r1, [r1, #4] /* r1 <- symbol value */
192 add r1, r1, r9 /* r1 <- relocated sym addr */
195 /* relative fix: increase location by offset */
200 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
210 .word __rel_dyn_start - _start
212 .word __rel_dyn_end - _start
214 .word __dynsym_start - _start
216 .globl c_runtime_cpu_setup
222 *************************************************************************
224 * CPU_init_critical registers
226 * setup important registers
227 * setup memory timing
229 *************************************************************************
232 #define INTCON (0x01c00000+0x200000)
233 #define INTMSK (0x01c00000+0x20000c)
234 #define LOCKTIME (0x01c00000+0x18000c)
235 #define PLLCON (0x01c00000+0x180000)
236 #define CLKCON (0x01c00000+0x180004)
237 #define WTCON (0x01c00000+0x130000)
239 /* disable watch dog */
245 * mask all IRQs by clearing all bits in the INTMRs
255 /* Set Clock Control Register */
262 #if CONFIG_S3C44B0_CLOCK_SPEED==66
263 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
264 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
265 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
267 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
279 /*************************************************/
280 /* interrupt vectors */
281 /*************************************************/
284 b undefined_instruction
292 /*************************************************/
294 undefined_instruction:
311 /* we *should* never reach this */