2 * Startup Code for S3C44B0 CPU-core
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30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 .word CONFIG_SYS_TEXT_BASE
69 #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
76 * These are defined in the board-specific linker script.
87 /* IRQ stack memory (calculated at run-time) */
88 .globl IRQ_STACK_START
92 /* IRQ stack memory (calculated at run-time) */
93 .globl FIQ_STACK_START
98 #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
99 /* IRQ stack memory (calculated at run-time) + 8 bytes */
100 .globl IRQ_STACK_START_IN
104 .globl _datarel_start
106 .word __datarel_start
108 .globl _datarelrolocal_start
109 _datarelrolocal_start:
110 .word __datarelrolocal_start
112 .globl _datarellocal_start
114 .word __datarellocal_start
116 .globl _datarelro_start
118 .word __datarelro_start
129 * the actual reset code
134 * set the cpu to SVC32 mode
142 * we do sys-critical inits only at reboot,
143 * not when booting from ram!
145 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
148 * before relocating, we have to setup RAM timing
149 * because memory timing is board-dependend, you will
150 * find a lowlevel_init.S in your board directory.
155 /* Set stackpointer in internal RAM to call board_init_f */
157 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
161 /*------------------------------------------------------------------------------*/
164 * void relocate_code (addr_sp, gd, addr_moni)
166 * This "function" does not return, instead it continues in RAM
167 * after relocating the monitor code.
172 mov r4, r0 /* save addr_sp */
173 mov r5, r1 /* save addr of gd */
174 mov r6, r2 /* save addr of destination */
175 mov r7, r2 /* save addr of destination */
177 /* Set up the stack */
184 sub r2, r3, r2 /* r2 <- size of armboot */
185 add r2, r0, r2 /* r2 <- source end address */
189 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
191 ldmia r0!, {r9-r10} /* copy from source address [r0] */
192 stmia r6!, {r9-r10} /* copy to target address [r1] */
193 cmp r0, r2 /* until source end address [r2] */
196 #ifndef CONFIG_PRELOADER
197 /* fix got entries */
198 ldr r1, _TEXT_BASE /* Text base */
199 mov r0, r7 /* reloc addr */
200 ldr r2, _got_start /* addr in Flash */
201 ldr r3, _got_end /* addr in Flash */
217 now copy to sram the interrupt vector
228 #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
231 #ifndef CONFIG_PRELOADER
234 ldr r3, _TEXT_BASE /* Text base */
235 mov r4, r7 /* reloc addr */
240 mov r2, #0x00000000 /* clear */
242 clbss_l:str r2, [r0] /* clear loop... */
252 * We are done. Do not return, instead branch to second part of board
253 * initialization, now running from RAM.
256 ldr r2, _board_init_r
258 add r2, r2, r7 /* position from board_init_r in RAM */
259 /* setup parameters for board_init_r */
260 mov r0, r5 /* gd_t */
261 mov r1, r7 /* dest_addr */
266 _board_init_r: .word board_init_r
268 #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
270 * the actual reset code
275 * set the cpu to SVC32 mode
283 * we do sys-critical inits only at reboot,
284 * not when booting from ram!
287 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
290 * before relocating, we have to setup RAM timing
291 * because memory timing is board-dependend, you will
292 * find a lowlevel_init.S in your board directory.
297 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
298 relocate: /* relocate U-Boot to RAM */
299 adr r0, _start /* r0 <- current position of code */
300 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
301 cmp r0, r1 /* don't reloc during debug */
304 ldr r2, _armboot_start
306 sub r2, r3, r2 /* r2 <- size of armboot */
307 add r2, r0, r2 /* r2 <- source end address */
310 ldmia r0!, {r3-r10} /* copy from source address [r0] */
311 stmia r1!, {r3-r10} /* copy to target address [r1] */
312 cmp r0, r2 /* until source end address [r2] */
316 now copy to sram the interrupt vector
327 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
329 /* Set up the stack */
331 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
332 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
333 sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
334 #ifdef CONFIG_USE_IRQ
335 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
337 sub sp, r0, #12 /* leave 3 words for abort-stack */
338 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
340 ldr pc, _start_armboot
342 _start_armboot: .word start_armboot
344 #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
347 *************************************************************************
349 * CPU_init_critical registers
351 * setup important registers
352 * setup memory timing
354 *************************************************************************
357 #define INTCON (0x01c00000+0x200000)
358 #define INTMSK (0x01c00000+0x20000c)
359 #define LOCKTIME (0x01c00000+0x18000c)
360 #define PLLCON (0x01c00000+0x180000)
361 #define CLKCON (0x01c00000+0x180004)
362 #define WTCON (0x01c00000+0x130000)
364 /* disable watch dog */
370 * mask all IRQs by clearing all bits in the INTMRs
380 /* Set Clock Control Register */
387 #if CONFIG_S3C44B0_CLOCK_SPEED==66
388 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
389 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
390 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
392 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
404 /*************************************************/
405 /* interrupt vectors */
406 /*************************************************/
409 b undefined_instruction
417 /*************************************************/
419 undefined_instruction:
436 /* we *should* never reach this */