2 * Startup Code for S3C44B0 CPU-core
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30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 .word CONFIG_SYS_TEXT_BASE
70 * These are defined in the board-specific linker script.
71 * Subtracting _start from them lets the linker put their
72 * relative position in the executable instead of leaving
77 .word __bss_start - _start
81 .word __bss_end__ - _start
88 /* IRQ stack memory (calculated at run-time) */
89 .globl IRQ_STACK_START
93 /* IRQ stack memory (calculated at run-time) */
94 .globl FIQ_STACK_START
99 /* IRQ stack memory (calculated at run-time) + 8 bytes */
100 .globl IRQ_STACK_START_IN
105 * the actual reset code
110 * set the cpu to SVC32 mode
118 * we do sys-critical inits only at reboot,
119 * not when booting from ram!
121 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
124 * before relocating, we have to setup RAM timing
125 * because memory timing is board-dependend, you will
126 * find a lowlevel_init.S in your board directory.
131 /* Set stackpointer in internal RAM to call board_init_f */
133 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
134 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
138 /*------------------------------------------------------------------------------*/
141 * void relocate_code (addr_sp, gd, addr_moni)
143 * This "function" does not return, instead it continues in RAM
144 * after relocating the monitor code.
149 mov r4, r0 /* save addr_sp */
150 mov r5, r1 /* save addr of gd */
151 mov r6, r2 /* save addr of destination */
153 /* Set up the stack */
159 beq clear_bss /* skip relocation */
160 mov r1, r6 /* r1 <- scratch for copy_loop */
161 ldr r3, _bss_start_ofs
162 add r2, r0, r3 /* r2 <- source end address */
165 ldmia r0!, {r9-r10} /* copy from source address [r0] */
166 stmia r1!, {r9-r10} /* copy to target address [r1] */
167 cmp r0, r2 /* until source end address [r2] */
170 #ifndef CONFIG_SPL_BUILD
172 * fix .rel.dyn relocations
174 ldr r0, _TEXT_BASE /* r0 <- Text base */
175 sub r9, r6, r0 /* r9 <- relocation offset */
176 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
177 add r10, r10, r0 /* r10 <- sym table in FLASH */
178 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
179 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
180 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
181 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
183 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
184 add r0, r0, r9 /* r0 <- location to fix up in RAM */
187 cmp r7, #23 /* relative fixup? */
189 cmp r7, #2 /* absolute fixup? */
191 /* ignore unknown type of fixup */
194 /* absolute fix: set location to (offset) symbol value */
195 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
196 add r1, r10, r1 /* r1 <- address of symbol in table */
197 ldr r1, [r1, #4] /* r1 <- symbol value */
198 add r1, r1, r9 /* r1 <- relocated sym addr */
201 /* relative fix: increase location by offset */
206 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
212 #ifndef CONFIG_SPL_BUILD
213 ldr r0, _bss_start_ofs
215 mov r4, r6 /* reloc addr */
218 mov r2, #0x00000000 /* clear */
220 clbss_l:str r2, [r0] /* clear loop... */
230 * We are done. Do not return, instead branch to second part of board
231 * initialization, now running from RAM.
233 ldr r0, _board_init_r_ofs
237 /* setup parameters for board_init_r */
238 mov r0, r5 /* gd_t */
239 mov r1, r6 /* dest_addr */
244 .word board_init_r - _start
247 .word __rel_dyn_start - _start
249 .word __rel_dyn_end - _start
251 .word __dynsym_start - _start
254 *************************************************************************
256 * CPU_init_critical registers
258 * setup important registers
259 * setup memory timing
261 *************************************************************************
264 #define INTCON (0x01c00000+0x200000)
265 #define INTMSK (0x01c00000+0x20000c)
266 #define LOCKTIME (0x01c00000+0x18000c)
267 #define PLLCON (0x01c00000+0x180000)
268 #define CLKCON (0x01c00000+0x180004)
269 #define WTCON (0x01c00000+0x130000)
271 /* disable watch dog */
277 * mask all IRQs by clearing all bits in the INTMRs
287 /* Set Clock Control Register */
294 #if CONFIG_S3C44B0_CLOCK_SPEED==66
295 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
296 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
297 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
299 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
311 /*************************************************/
312 /* interrupt vectors */
313 /*************************************************/
316 b undefined_instruction
324 /*************************************************/
326 undefined_instruction:
343 /* we *should* never reach this */