2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm-offsets.h>
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
77 .word CONFIG_SYS_TEXT_BASE
80 * These are defined in the board-specific linker script.
81 * Subtracting _start from them lets the linker put their
82 * relative position in the executable instead of leaving
87 .word __bss_start - _start
91 .word __bss_end__ - _start
98 /* IRQ stack memory (calculated at run-time) */
99 .globl IRQ_STACK_START
103 /* IRQ stack memory (calculated at run-time) */
104 .globl FIQ_STACK_START
109 /* IRQ stack memory (calculated at run-time) + 8 bytes */
110 .globl IRQ_STACK_START_IN
115 * the actual reset code
120 * set the cpu to SVC32 mode
128 * we do sys-critical inits only at reboot,
129 * not when booting from ram!
131 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
135 /* Set stackpointer in internal RAM to call board_init_f */
137 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
138 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
142 /*------------------------------------------------------------------------------*/
145 * void relocate_code (addr_sp, gd, addr_moni)
147 * This "function" does not return, instead it continues in RAM
148 * after relocating the monitor code.
153 mov r4, r0 /* save addr_sp */
154 mov r5, r1 /* save addr of gd */
155 mov r6, r2 /* save addr of destination */
157 /* Set up the stack */
163 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
164 beq clear_bss /* skip relocation */
165 mov r1, r6 /* r1 <- scratch for copy_loop */
166 ldr r3, _bss_start_ofs
167 add r2, r0, r3 /* r2 <- source end address */
170 ldmia r0!, {r9-r10} /* copy from source address [r0] */
171 stmia r1!, {r9-r10} /* copy to target address [r1] */
172 cmp r0, r2 /* until source end address [r2] */
175 #ifndef CONFIG_SPL_BUILD
177 * fix .rel.dyn relocations
179 ldr r0, _TEXT_BASE /* r0 <- Text base */
180 sub r9, r6, r0 /* r9 <- relocation offset */
181 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
182 add r10, r10, r0 /* r10 <- sym table in FLASH */
183 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
184 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
185 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
186 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
188 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
189 add r0, r0, r9 /* r0 <- location to fix up in RAM */
192 cmp r7, #23 /* relative fixup? */
194 cmp r7, #2 /* absolute fixup? */
196 /* ignore unknown type of fixup */
199 /* absolute fix: set location to (offset) symbol value */
200 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
201 add r1, r10, r1 /* r1 <- address of symbol in table */
202 ldr r1, [r1, #4] /* r1 <- symbol value */
203 add r1, r1, r9 /* r1 <- relocated sym addr */
206 /* relative fix: increase location by offset */
211 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
217 #ifndef CONFIG_SPL_BUILD
218 ldr r0, _bss_start_ofs
220 mov r4, r6 /* reloc addr */
223 mov r2, #0x00000000 /* clear */
225 clbss_l:cmp r0, r1 /* clear loop... */
226 bhs clbss_e /* if reached end of bss, exit */
234 * We are done. Do not return, instead branch to second part of board
235 * initialization, now running from RAM.
237 ldr r0, _board_init_r_ofs
241 /* setup parameters for board_init_r */
242 mov r0, r5 /* gd_t */
243 mov r1, r6 /* dest_addr */
248 .word board_init_r - _start
251 .word __rel_dyn_start - _start
253 .word __rel_dyn_end - _start
255 .word __dynsym_start - _start
258 *************************************************************************
260 * CPU_init_critical registers
262 * setup important registers
263 * setup memory timing
265 *************************************************************************
269 /* Interrupt-Controller base address */
270 IC_BASE: .word 0x90050000
274 /* Reset-Controller */
275 RST_BASE: .word 0x90030000
281 PWR_BASE: .word 0x90020000
284 cpuspeed: .word CONFIG_SYS_CPUSPEED
295 /* set clock speed */
301 * before relocating, we have to setup RAM timing
302 * because memory timing is board-dependend, you will
303 * find a lowlevel_init.S in your board directory.
310 * disable MMU stuff and enable I-cache
313 bic r0, r0, #0x00002000 @ clear bit 13 (X)
314 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
315 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
316 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
320 * flush v4 I/D caches
323 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
324 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
330 *************************************************************************
334 *************************************************************************
340 #define S_FRAME_SIZE 72
362 #define MODE_SVC 0x13
366 * use bad_save_user_regs for abort/prefetch/undef/swi ...
367 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
370 .macro bad_save_user_regs
371 sub sp, sp, #S_FRAME_SIZE
372 stmia sp, {r0 - r12} @ Calling r0-r12
375 ldr r2, IRQ_STACK_START_IN
376 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
377 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
381 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
385 .macro irq_save_user_regs
386 sub sp, sp, #S_FRAME_SIZE
387 stmia sp, {r0 - r12} @ Calling r0-r12
389 stmdb r8, {sp, lr}^ @ Calling SP, LR
390 str lr, [r8, #0] @ Save calling PC
392 str r6, [r8, #4] @ Save CPSR
393 str r0, [r8, #8] @ Save OLD_R0
397 .macro irq_restore_user_regs
398 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
400 ldr lr, [sp, #S_PC] @ Get PC
401 add sp, sp, #S_FRAME_SIZE
402 subs pc, lr, #4 @ return & move spsr_svc into cpsr
406 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
408 str lr, [r13] @ save caller lr / spsr
412 mov r13, #MODE_SVC @ prepare SVC-Mode
418 .macro get_irq_stack @ setup IRQ stack
419 ldr sp, IRQ_STACK_START
422 .macro get_fiq_stack @ setup FIQ stack
423 ldr sp, FIQ_STACK_START
430 undefined_instruction:
433 bl do_undefined_instruction
439 bl do_software_interrupt
459 #ifdef CONFIG_USE_IRQ
466 irq_restore_user_regs
471 /* someone ought to write a more effiction fiq_save_user_regs */
474 irq_restore_user_regs
496 mov r1, #0x0 @ set bit 3-0 ...
497 str r1, [r0, #RCSR] @ ... to clear in RCSR
499 str r1, [r0, #RSRR] @ and perform reset
500 b reset_cpu @ silly, but repeat endlessly