2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
16 *************************************************************************
18 * Startup Code (reset vector)
20 * do important init only if we don't start from memory!
21 * relocate armboot to ram
23 * jump to second stage
25 *************************************************************************
32 * set the cpu to SVC32 mode
40 * we do sys-critical inits only at reboot,
41 * not when booting from ram!
43 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
49 /*------------------------------------------------------------------------------*/
51 .globl c_runtime_cpu_setup
57 *************************************************************************
59 * CPU_init_critical registers
61 * setup important registers
64 *************************************************************************
68 /* Interrupt-Controller base address */
69 IC_BASE: .word 0x90050000
73 /* Reset-Controller */
74 RST_BASE: .word 0x90030000
80 PWR_BASE: .word 0x90020000
83 cpuspeed: .word CONFIG_SYS_CPUSPEED
100 * before relocating, we have to setup RAM timing
101 * because memory timing is board-dependend, you will
102 * find a lowlevel_init.S in your board directory.
109 * disable MMU stuff and enable I-cache
112 bic r0, r0, #0x00002000 @ clear bit 13 (X)
113 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
114 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
115 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
119 * flush v4 I/D caches
122 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
123 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */