2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
17 *************************************************************************
19 * Startup Code (reset vector)
21 * do important init only if we don't start from memory!
22 * relocate armboot to ram
24 * jump to second stage
26 *************************************************************************
33 * set the cpu to SVC32 mode
41 * we do sys-critical inits only at reboot,
42 * not when booting from ram!
44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
50 /*------------------------------------------------------------------------------*/
52 .globl c_runtime_cpu_setup
58 *************************************************************************
60 * CPU_init_critical registers
62 * setup important registers
65 *************************************************************************
69 /* Interrupt-Controller base address */
70 IC_BASE: .word 0x90050000
74 /* Reset-Controller */
75 RST_BASE: .word 0x90030000
81 PWR_BASE: .word 0x90020000
84 cpuspeed: .word CONFIG_SYS_CPUSPEED
101 * before relocating, we have to setup RAM timing
102 * because memory timing is board-dependend, you will
103 * find a lowlevel_init.S in your board directory.
110 * disable MMU stuff and enable I-cache
113 bic r0, r0, #0x00002000 @ clear bit 13 (X)
114 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
115 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
116 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
120 * flush v4 I/D caches
123 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
124 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */