2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm-offsets.h>
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
77 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
78 .word CONFIG_SPL_TEXT_BASE
80 .word CONFIG_SYS_TEXT_BASE
84 * These are defined in the board-specific linker script.
85 * Subtracting _start from them lets the linker put their
86 * relative position in the executable instead of leaving
91 .word __bss_start - _start
95 .word __bss_end - _start
101 #ifdef CONFIG_USE_IRQ
102 /* IRQ stack memory (calculated at run-time) */
103 .globl IRQ_STACK_START
107 /* IRQ stack memory (calculated at run-time) */
108 .globl FIQ_STACK_START
113 /* IRQ stack memory (calculated at run-time) + 8 bytes */
114 .globl IRQ_STACK_START_IN
119 * the actual reset code
124 * set the cpu to SVC32 mode
132 * we do sys-critical inits only at reboot,
133 * not when booting from ram!
135 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
141 /*------------------------------------------------------------------------------*/
143 .globl c_runtime_cpu_setup
149 *************************************************************************
151 * CPU_init_critical registers
153 * setup important registers
154 * setup memory timing
156 *************************************************************************
160 /* Interrupt-Controller base address */
161 IC_BASE: .word 0x90050000
165 /* Reset-Controller */
166 RST_BASE: .word 0x90030000
172 PWR_BASE: .word 0x90020000
175 cpuspeed: .word CONFIG_SYS_CPUSPEED
186 /* set clock speed */
192 * before relocating, we have to setup RAM timing
193 * because memory timing is board-dependend, you will
194 * find a lowlevel_init.S in your board directory.
201 * disable MMU stuff and enable I-cache
204 bic r0, r0, #0x00002000 @ clear bit 13 (X)
205 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
206 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
207 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
211 * flush v4 I/D caches
214 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
215 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
221 *************************************************************************
225 *************************************************************************
231 #define S_FRAME_SIZE 72
253 #define MODE_SVC 0x13
257 * use bad_save_user_regs for abort/prefetch/undef/swi ...
258 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
261 .macro bad_save_user_regs
262 sub sp, sp, #S_FRAME_SIZE
263 stmia sp, {r0 - r12} @ Calling r0-r12
266 ldr r2, IRQ_STACK_START_IN
267 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
268 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
272 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
276 .macro irq_save_user_regs
277 sub sp, sp, #S_FRAME_SIZE
278 stmia sp, {r0 - r12} @ Calling r0-r12
280 stmdb r8, {sp, lr}^ @ Calling SP, LR
281 str lr, [r8, #0] @ Save calling PC
283 str r6, [r8, #4] @ Save CPSR
284 str r0, [r8, #8] @ Save OLD_R0
288 .macro irq_restore_user_regs
289 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
291 ldr lr, [sp, #S_PC] @ Get PC
292 add sp, sp, #S_FRAME_SIZE
293 subs pc, lr, #4 @ return & move spsr_svc into cpsr
297 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
299 str lr, [r13] @ save caller lr / spsr
303 mov r13, #MODE_SVC @ prepare SVC-Mode
309 .macro get_irq_stack @ setup IRQ stack
310 ldr sp, IRQ_STACK_START
313 .macro get_fiq_stack @ setup FIQ stack
314 ldr sp, FIQ_STACK_START
321 undefined_instruction:
324 bl do_undefined_instruction
330 bl do_software_interrupt
350 #ifdef CONFIG_USE_IRQ
357 irq_restore_user_regs
362 /* someone ought to write a more effiction fiq_save_user_regs */
365 irq_restore_user_regs
387 mov r1, #0x0 @ set bit 3-0 ...
388 str r1, [r0, #RCSR] @ ... to clear in RCSR
390 str r1, [r0, #RSRR] @ and perform reset
391 b reset_cpu @ silly, but repeat endlessly