2 * armboot - Startup Code for SA1100 CPU
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
9 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
17 *************************************************************************
19 * Jump vector table as in table 3.1 in [1]
21 *************************************************************************
27 ldr pc, _undefined_instruction
28 ldr pc, _software_interrupt
29 ldr pc, _prefetch_abort
35 _undefined_instruction: .word undefined_instruction
36 _software_interrupt: .word software_interrupt
37 _prefetch_abort: .word prefetch_abort
38 _data_abort: .word data_abort
39 _not_used: .word not_used
43 .balignl 16,0xdeadbeef
47 *************************************************************************
49 * Startup Code (reset vector)
51 * do important init only if we don't start from memory!
52 * relocate armboot to ram
54 * jump to second stage
56 *************************************************************************
60 /* IRQ stack memory (calculated at run-time) */
61 .globl IRQ_STACK_START
65 /* IRQ stack memory (calculated at run-time) */
66 .globl FIQ_STACK_START
71 /* IRQ stack memory (calculated at run-time) + 8 bytes */
72 .globl IRQ_STACK_START_IN
77 * the actual reset code
82 * set the cpu to SVC32 mode
90 * we do sys-critical inits only at reboot,
91 * not when booting from ram!
93 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
99 /*------------------------------------------------------------------------------*/
101 .globl c_runtime_cpu_setup
107 *************************************************************************
109 * CPU_init_critical registers
111 * setup important registers
112 * setup memory timing
114 *************************************************************************
118 /* Interrupt-Controller base address */
119 IC_BASE: .word 0x90050000
123 /* Reset-Controller */
124 RST_BASE: .word 0x90030000
130 PWR_BASE: .word 0x90020000
133 cpuspeed: .word CONFIG_SYS_CPUSPEED
144 /* set clock speed */
150 * before relocating, we have to setup RAM timing
151 * because memory timing is board-dependend, you will
152 * find a lowlevel_init.S in your board directory.
159 * disable MMU stuff and enable I-cache
162 bic r0, r0, #0x00002000 @ clear bit 13 (X)
163 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
164 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
165 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
169 * flush v4 I/D caches
172 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
173 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
179 *************************************************************************
183 *************************************************************************
189 #define S_FRAME_SIZE 72
211 #define MODE_SVC 0x13
215 * use bad_save_user_regs for abort/prefetch/undef/swi ...
216 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
219 .macro bad_save_user_regs
220 sub sp, sp, #S_FRAME_SIZE
221 stmia sp, {r0 - r12} @ Calling r0-r12
224 ldr r2, IRQ_STACK_START_IN
225 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
226 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
230 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
234 .macro irq_save_user_regs
235 sub sp, sp, #S_FRAME_SIZE
236 stmia sp, {r0 - r12} @ Calling r0-r12
238 stmdb r8, {sp, lr}^ @ Calling SP, LR
239 str lr, [r8, #0] @ Save calling PC
241 str r6, [r8, #4] @ Save CPSR
242 str r0, [r8, #8] @ Save OLD_R0
246 .macro irq_restore_user_regs
247 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
249 ldr lr, [sp, #S_PC] @ Get PC
250 add sp, sp, #S_FRAME_SIZE
251 subs pc, lr, #4 @ return & move spsr_svc into cpsr
255 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
257 str lr, [r13] @ save caller lr / spsr
261 mov r13, #MODE_SVC @ prepare SVC-Mode
267 .macro get_irq_stack @ setup IRQ stack
268 ldr sp, IRQ_STACK_START
271 .macro get_fiq_stack @ setup FIQ stack
272 ldr sp, FIQ_STACK_START
279 undefined_instruction:
282 bl do_undefined_instruction
288 bl do_software_interrupt
308 #ifdef CONFIG_USE_IRQ
315 irq_restore_user_regs
320 /* someone ought to write a more effiction fiq_save_user_regs */
323 irq_restore_user_regs
345 mov r1, #0x0 @ set bit 3-0 ...
346 str r1, [r0, #RCSR] @ ... to clear in RCSR
348 str r1, [r0, #RSRR] @ and perform reset
349 b reset_cpu @ silly, but repeat endlessly