2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra AP (Application Processor) code */
12 #include <asm/arch/gp_padctrl.h>
13 #include <asm/arch-tegra/ap.h>
14 #include <asm/arch-tegra/clock.h>
15 #include <asm/arch-tegra/fuse.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/scu.h>
18 #include <asm/arch-tegra/tegra.h>
19 #include <asm/arch-tegra/warmboot.h>
21 int tegra_get_chip(void)
24 struct apb_misc_gp_ctlr *gp =
25 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
28 * This is undocumented, Chip ID is bits 15:8 of the register
29 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
30 * Tegra30, and 0x35 for T114.
32 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
33 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
38 int tegra_get_sku_info(void)
41 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
43 sku_id = readl(&fuse->sku_info) & 0xff;
44 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
49 int tegra_get_chip_sku(void)
53 chip_id = tegra_get_chip();
54 sku_id = tegra_get_sku_info();
74 case SKU_ID_TM30MQS_P_A3:
82 return TEGRA_SOC_T114;
86 /* unknown chip/sku id */
87 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
88 __func__, chip_id, sku_id);
89 return TEGRA_SOC_UNKNOWN;
92 static void enable_scu(void)
94 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
97 /* Only enable the SCU on T20/T25 */
98 if (tegra_get_chip() != CHIPID_TEGRA20)
101 /* If SCU already setup/enabled, return */
102 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
105 /* Invalidate all ways for all processors */
106 writel(0xFFFF, &scu->scu_inv_all);
108 /* Enable SCU - bit 0 */
109 reg = readl(&scu->scu_ctrl);
110 reg |= SCU_CTRL_ENABLE;
111 writel(reg, &scu->scu_ctrl);
114 static u32 get_odmdata(void)
117 * ODMDATA is stored in the BCT in IRAM by the BootROM.
118 * The BCT start and size are stored in the BIT in IRAM.
119 * Read the data @ bct_start + (bct_size - 12). This works
120 * on T20 and T30 BCTs, which are locked down. If this changes
121 * in new chips (T114, etc.), we can revisit this algorithm.
124 u32 bct_start, odmdata;
126 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
127 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
132 static void init_pmc_scratch(void)
134 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
138 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
139 for (i = 0; i < 23; i++)
140 writel(0, &pmc->pmc_scratch1+i);
142 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
143 odmdata = get_odmdata();
144 writel(odmdata, &pmc->pmc_scratch20);
149 /* Init PMC scratch memory */