2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/gp_padctrl.h>
26 #include <asm/arch-tegra/ap.h>
27 #include <asm/arch-tegra/fuse.h>
28 #include <asm/arch-tegra/pmc.h>
29 #include <asm/arch-tegra/scu.h>
30 #include <asm/arch-tegra/warmboot.h>
32 int tegra_get_chip_type(void)
34 struct apb_misc_gp_ctlr *gp;
35 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
36 uint tegra_sku_id, rev;
39 * This is undocumented, Chip ID is bits 15:8 of the register
40 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
43 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
44 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
46 tegra_sku_id = readl(&fuse->sku_info) & 0xff;
50 switch (tegra_sku_id) {
63 return TEGRA_SOC_UNKNOWN;
66 static void enable_scu(void)
68 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
71 /* If SCU already setup/enabled, return */
72 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
75 /* Invalidate all ways for all processors */
76 writel(0xFFFF, &scu->scu_inv_all);
78 /* Enable SCU - bit 0 */
79 reg = readl(&scu->scu_ctrl);
80 reg |= SCU_CTRL_ENABLE;
81 writel(reg, &scu->scu_ctrl);
84 static u32 get_odmdata(void)
87 * ODMDATA is stored in the BCT in IRAM by the BootROM.
88 * The BCT start and size are stored in the BIT in IRAM.
89 * Read the data @ bct_start + (bct_size - 12). This works
90 * on T20 and T30 BCTs, which are locked down. If this changes
91 * in new chips (T114, etc.), we can revisit this algorithm.
94 u32 bct_start, odmdata;
96 bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
97 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
102 static void init_pmc_scratch(void)
104 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
108 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
109 for (i = 0; i < 23; i++)
110 writel(0, &pmc->pmc_scratch1+i);
112 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
113 odmdata = get_odmdata();
114 writel(odmdata, &pmc->pmc_scratch20);
119 /* Init PMC scratch memory */
124 /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
126 "mrc p15, 0, r0, c1, c0, 1\n"
127 "orr r0, r0, #0x41\n"
128 "mcr p15, 0, r0, c1, c0, 1\n");
130 /* FIXME: should have ap20's L2 disabled too? */