2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* Tegra AP (Application Processor) code */
28 #include <asm/arch/gp_padctrl.h>
29 #include <asm/arch-tegra/ap.h>
30 #include <asm/arch-tegra/clock.h>
31 #include <asm/arch-tegra/fuse.h>
32 #include <asm/arch-tegra/pmc.h>
33 #include <asm/arch-tegra/scu.h>
34 #include <asm/arch-tegra/tegra.h>
35 #include <asm/arch-tegra/warmboot.h>
37 int tegra_get_chip(void)
40 struct apb_misc_gp_ctlr *gp =
41 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
44 * This is undocumented, Chip ID is bits 15:8 of the register
45 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
46 * Tegra30, and 0x35 for T114.
48 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
49 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
54 int tegra_get_sku_info(void)
57 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
59 sku_id = readl(&fuse->sku_info) & 0xff;
60 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
65 int tegra_get_chip_sku(void)
69 chip_id = tegra_get_chip();
70 sku_id = tegra_get_sku_info();
97 return TEGRA_SOC_T114;
101 /* unknown chip/sku id */
102 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
103 __func__, chip_id, sku_id);
104 return TEGRA_SOC_UNKNOWN;
107 static void enable_scu(void)
109 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
112 /* Only enable the SCU on T20/T25 */
113 if (tegra_get_chip() != CHIPID_TEGRA20)
116 /* If SCU already setup/enabled, return */
117 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
120 /* Invalidate all ways for all processors */
121 writel(0xFFFF, &scu->scu_inv_all);
123 /* Enable SCU - bit 0 */
124 reg = readl(&scu->scu_ctrl);
125 reg |= SCU_CTRL_ENABLE;
126 writel(reg, &scu->scu_ctrl);
129 static u32 get_odmdata(void)
132 * ODMDATA is stored in the BCT in IRAM by the BootROM.
133 * The BCT start and size are stored in the BIT in IRAM.
134 * Read the data @ bct_start + (bct_size - 12). This works
135 * on T20 and T30 BCTs, which are locked down. If this changes
136 * in new chips (T114, etc.), we can revisit this algorithm.
139 u32 bct_start, odmdata;
141 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
142 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
147 static void init_pmc_scratch(void)
149 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
153 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
154 for (i = 0; i < 23; i++)
155 writel(0, &pmc->pmc_scratch1+i);
157 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
158 odmdata = get_odmdata();
159 writel(odmdata, &pmc->pmc_scratch20);
164 /* Init PMC scratch memory */